* All publications co-authored with members in Professor Jason Cong's research
group lists co-authors in alphabetical order.
Book Chapters and Journal Papers
J. Cong, J. Fang, M. Xie, and Y. Zhang, "MARS
- A Multilevel Full-Chip Gridless Routing System," IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24,
No. 3, pp. 382-394, March 2005.
J. Cong, M. Xie, and Y. Zhang, "Chapter 5 Multilevel VLSI Routing,"
Multilevel
Optimization in VLSICAD, Kluwer Academic Publishers, 2003.
Yiqian Zhang, Y. Cai, X. Hong, Y. Zhang and X. Min, "A Gridless Router
Based on Hierarchical PB Corner Stitching Structure", The Chinese Journal
of Semiconductors, vol. 24, 2003. (in Chinese)
Y. Zhang, B. Wang, Y. Cai and X. Hong, "Area Routing Oriented Hierarchical
Corner Stitching with Partial Bin," The Chinese Journal of Computers,
vol.
7, 2000. (in Chinese)
Yiqian Zhang, Yan Zhang, Y. Cai and X. Hong, "An algorithm for bus routing
based on line-probe," Microelectronics, S0:13, 2000. (in Chinese)
B. Wang, Y. Zhang, Y. Cai and X. Hong, "A Layer Assignment Algorithm for
Congestion and Via Minimization," Microelectronics, S0:13,
2000. (in Chinese)
Conference Publications
J. Cong, J. Wei and Y. Zhang, "Thermal-Aware 3D IC Placement Via Transformation,"
submitted to DAC 2006.
J. Cong and Y. Zhang, " Thermal Via Planning
for 3-D IC's, " Proceedings of the 2005 IEEE/ACM International
Conference on Computer Aided Design, San Jose, CA, November, 2005.
J. Cong, M. Xie and Y. Zhang, "An
Enhanced Multilevel Routing System,"Proceedings
of the International Conference on Computer-Aided Design, November
2002.
J. Cong, J. Fang and Y. Zhang, "Multilevel Approach
to Full-Chip Gridless Routing," Proceedings of the IEEE International
Conference on Computer Aided Design, San Jose, California, pp. 396-403,
November 2001.
Y. Zhang, B. Wang, Y. Cai and X. Hong, "Area Routing Oriented Hierarchical
Corner Stitching with Partial Bin," Proceedings
of the Asia South Pacific Design Automation Conference,2000.
