Zhiru Zhang

PhD candidate in UCLA Computer Science Department

Graduate Research Assistant

Advisor: Prof. Jason Cong

RESEARCH INTERESTS

(1) Platform-based hardware/software co-design for embedded systems

Currently working on the Pilot system which aims to effectively map a system-level design specification onto a given SoC platform, in particular, the field programmable SoC platform.

(2) Communication-centric high-level synthesis

Developed the MCAS system (Architectural Synthesis system for Multi-cycle Communication) to efficiently synthesize the behavioral descriptions onto the RDR micro-architecture (Regular Distributed Register Architecture).

(3) Compilation techniques for reconfigurable systems

Developed a set of novel extended instruction generation techniques for ASIPs.

PUBLICATIONS

Journal Publication

[1] Architecture and Synthesis for Multi-Cycle On-Chip Communication, (co-authored with J. Cong, Y. Fan, G. Han, and X. Yang), Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computer-Aided Design of Integrate d Circuits and Systems, pp. 550-564, Apr. 2004. [pdf]

Conference Publications

[1] Pilot --- A Platform-Based HW/SW Synthesis System for FPSoC, (co-authored with Z. Chen, J. Cong, Y. Fan, and X. Yang,) in Proceedings of 2003 Workshop on Software Support for Reconfigurable Systems, Apr. 2003. [pdf]

[2] Architecture and Synthesis for Multi-Cycle Communication, (co-authored with J. Cong, Y. Fan, and X. Yang,) in Proceedings of 2003 International Symposium on Physical Design, pp. 190-196, Apr. 2003. [pdf]

[3] Architecture and Synthesis for Multi-Cycle On-Chip Communication (Extended Abstract), (co-authored with J. Cong, Y. Fan, G. Han, and X. Yang,) in Proceedings of First International Conference on Hardware/Software Codesign & System Synthesis, pp. 77-78, Oct. 2003. [pdf]

[4] Gradual Relaxation Techniques with Applications to Behavioral Synthesis, (co-authored with Y. Fan, M. Potkonjak, and J. Cong,) in Proceedings of International Conference on Computer Aided Design, pp. 529-535, Nov. 2003. [pdf]

[5] Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication, (co-authored with J. Cong, Y. Fan, G. Han, and X. Yang,) in Proceedings of International Conference on Computer Aided Design, pp 536-543, Nov. 2003. [pdf]

[6] Application-Specific Instruction Generation for Configurable Processor Architectures, (co-authored with J. Cong, Y. Fan, and G. Han,) in Proceedings of International Symposium on Field Programmable Gate Arrays, pp. 183-189, Feb. 2004. [pdf]

[7] Architecture-Level Synthesis for Automatic Interconnect Pipelining, (co-authored with J. Cong and Y. Fan,) in Proceedings of 41^st Design Automation Conference, Jun. 2004. [pdf]

[8] Bitwidth-Aware Scheduling and Binding in High-Level Synthesis, (co-authored with J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, and X. Cheng,) in Proceedings of Asia South Pacific Design Automation Conference, pp. 856-861, Jan. 2005. [pdf]

[9] Instruction Set Extension with Shadow Registers for Configurable Processors, (co-authored with J. Cong, Y. Fan, G. Han, A. Jagannathan, and G. Reinman,) in Proceedings of International Symposium on Field-Programmable Gate Arrays, pp. 99-106, Feb. 2005. [pdf]

[10] xPilot: A Platform-Based Behavioral Synthesis System, (co-authored with D. Chen, J. Cong, Y. Fan, G. Han, and W. Jiang) in Proceedings of SRC Techcon Conference, Oct. 2005.

[11] Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors, (co-authored with J. Cong, G. Han) in Proceedings of International Conference on Computer Aided Design, pp. 263-270, Nov. 2005. [pdf]