Network-On-Chip Design with RF Interconnects for Future Chip Multi-Processors

Glenn Reinman and Jason Cong, UCLA Computer Science Department, reinman@cs.ucla.edu, (310) 794-9755
Frank Chang, UCLA Electrical Engineering Department
Needs Categories: S2.2 and S5.1

References:

[1] P. Abad, V. Puente, J.A. Greogorio, and P. Prieto, “Rotary Router: An Efficient Architecture for CMP Interconnection Networks,” in Proceedings of ISCA-34, June 2007.
[2] B. Beckmann and D. Wood, “TLC: Transmission Line Caches,” in Proceedings of MICRO-36, December 2003.
[3] B. Beckmann and D. Wood, “Managing Wire Delay in Large Chip-Multiprocessor Caches,” in Proceedings of MICRO-37, December 2004.
[4] L. Benini, G. De Micheli, "Networks on Chips: A New SoC Paradigm,” IEEE Computer, vol. 35, no. 1, Jan. 2002.
[5] M. F. Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, and Rocco Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. International Symposium on High-Performance Computer Architecture, Feb 2008.
[6] M.F. Chang, V.P. Roychowdhury, L. Zhang, H. Shin, Y. Qian, “RF/wireless interconnect for inter- and intra-chip communications,” in Proceedings of the IEEE, vol 89. no 4, April 2001.
[7] M. F. Chang, I. Verbauwhede, C. Chien, Z. Xu, J. Kim, J. Ko, Q. Gu, and B. Lai, “Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI communications,” in IEEE Transactions on Electron Devices, July 2005.
[8] L. Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian, J.B. Carter, “Interconnect-Aware Coherence Protocols for Chip Multiprocessors,” in Proceedings of ISCA-33, June 2006.
[9] D. Culler, J.P. Singh, A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufman Publishers Inc, San Francisco, CA, 1999.
[10] W.J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proceedings of Design Automation Conference (DAC), June 2001.
[11] J. Duato, “A Theory of Deadlock-Free Adaptive Multicast Routing in Wormhole Networks,” in IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 9, September 1995.
[12] C.J. Glass, L.M. Ni, “The Turn Model For Adaptive Routing,” in Proceedings of ISCA-19, May 1992.
[13] Q. Gu, Z. Xu, J. Ko and M.F. Chang, "Two 10Gbps/pin Low Power Interconnect Methods for 3D IC", 2007 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, vol.50, pp.448-449, Feb. 2007, San Francisco, California, USA
[14] M. Haurylau, G. Chen, H. Chen, J. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, " On-chip Optical Interconnect Roadmap: Challenges and Critical Directions, " IEEE Journal of Selected Topics in Quantum Electronics, Vol. 12, No. 6, pp. 1699-1705, November/December 2006
[15] R. Ho, K.W. Mai, and M. Horowitz, “The Future of Wires,” in Proceedings of the IEEE, vol 89. no 4, April 2001.
[16] D.Q. Huang, W. Hunt, N.Y. Wang, T. W. Ku, Q. Gu, R. Wong, and M. F. Chang, “A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction,” in 2006 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February, 2006,
[17] Y. Jin, E.J. Kim, and K.H. Yum, “A Domain-Specific On-Chip Network Design for Large Scale Cache Systems,” in Proceedings of HPCA-13, February 2007.
[18] Tanay Karnik, Shekhar Borkar, “Sub-90nm Technologies—Challenges and Opportunities for CAD”, Proceedings of International Conference on Computer Aided Design, November 2002.
[19] J. Kim, W.J. Dally, and D. Abts, “Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks,” in Proceedings of ISCA-34, June 2007.
[20] J.Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M.S. Yousif, C.R. Das, “A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures,” in Proceedings of ISCA-34, June 2007.
[21] N. Kirman, M. Kirman, R.K. Dokania, J.F. Martinez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi, “Leveraging Optical Technology in Future Bus-based Chip Multiprocessors,” In Proceedings of MICRO-39, December 2006.
[22] J. Ko, J. Kim, Z. Xu, Q. Gu, C. Chien, and M.F. Chang, “An RF/Baseband FDMA-Interconnect Transceiver for Reconfigurable Multiple Access Chip-to-Chip Communication,” in 2005 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February 2005.
[23] A. Kumar, L.S. Peh, P. Kundu, and N.K. Jha, “Express Virtual Channels: Towards the Ideal Interconnection Fabric,” in Proceedings of ISCA-34, June 2007.
[24] R. Kumar, V. Zyuban, D.M. Tullsen, “Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling,” in Proceedings of ISCA-32, June 2005.
[25] F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, “Design and Management of 3D Chip Multiprocessors Using Network-in-Memory,” in Proceedings of ISCA-33, June 2006.
[26] C.A. Nicopoulos, D. Park, J. Kim, R. Das, Y. Xie, N. Vijaykrishnan, M.S. Yousif, C. R. Das, “ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers,” in Proceedings of MICRO-39, December 2006.
[27] K.K. O, K. Kim, B.A. Floyd, J.L Mehta, H. Yoon, C. Hung, D. Bravo, T.O. Dickson, X. Guo, R. Li, T. N, J. Caserta, W.R. Bomstad, J. Branch, D. Tang, J. Bohorquez, E. Seok, G. Li, A. Sugavanam, J.-J Lin, J. Chen, J.E. Brewer, “On-Chip antennas in silicon ICs and their application,” in IEEE Transactions on Electron Devices, July 2005.
[28] U.Y. Ogras and R. Marculescu, “’It’s A Small World After All’: NoC Performance Optimization Via Long-Range Link Insertion,” in IEEE Transactions on VLSI Systems, vol. 14, no. 7, July 2006.
[29] J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos, “SESC Simulator,” Jan. 2005, http://sesc.sourceforge.net.
[30] Shacham, A.; Bergman, K.; Carloni, L.P., “On the Design of a Photonic Network-on-Chip,” IEEE NOCS 2007, pp. 53 - 64.
[31] Tam, Sai-Wang, Socher, E…, Chang, M.F., “Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communication”, submitted to 2008 ISSCC
[32] S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, “The Splash-2 Programs: Characterization and Methodological Considerations,” in Proceedings of ISCA-22, June 1995.
[33] International Technology Roadmap for Semiconductors: Semiconductor Industry Association, 2006
[34] http://www.engineer.ucla.edu/news/2007/Submillimeter%20Waves.html