Publications
1. J. Cong and J. Xu, "Simultaneous FU and Register Binding Based on Network Flow Method," Design, Automation and Test in Europe (DATE 2008), Munich, Germany, March 2008.
2. Y. Ma, X. Li, J. Cong, X. Hong, G. Reinman, S. Dong and Q. Zhou, "Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning," Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 920-925, January 2008.
3. J. Cong, Y. Ma, Y. Liu, E. Kursun, and G. Reinman, "3D Architecture Modeling and Exploration," Proceedings of 24th International VLSI/ULSI Multilevel Interconnection Conference (VMIC), Fremont, CA, pages 231-238, September 2007.
4. J. Cong, Y. Fan, and W. Jiang, "Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture," Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2006.
6. J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "Platform-Based Behavior-Level and System-Level Synthesis," Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006. (Invited Paper)
8. G. Chen and J. Cong, "Simultaneous Placement with Clustering and Duplication," ACM Transaction on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 740-772, July 2006.
9. J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang, "Behavior and Communication Co-Optimization for Systems with Sequential Communication Media," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.
10. J. Cong and Z. Zhang, "An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 433-438, July 2006.
13. D. Chen, J. Cong, and J. Xu, "Optimal Simultaneous Module and Multi-Voltage Assignment for Low-Power," ACM Transaction on Design Automation of Electronic Systems, vol. 11, Issue 2, pp. 362-386, April 2006.
15. J. Cong, A. Jagannathan, Y. Ma, G. Reinman and J. Wei, "An Automated Design Flow for 3D Microarchitecture Evaluation," Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Yokohama, Japan, pp.384-389, January 2006.
16. J. Xu, J. Cong and X. Cheng, "Lower-Bound Estimation for Multi-Bitwidth Scheduling," Proceedings of the International Symposium on Circuits and Systems, Kobe, Japan, pp. 856-861, May 2005.
17. J. Cong, G. Han and Z. Zhang, "Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors," Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 263-270, November 2005.
19. J. Cong, J. Fang, M. Xie, and Y. Zhang, "MARS - A Multilevel Full-Chip Gridless Routing System," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 382-394, March 2005.
20. C.T. Hsieh, J. Cong, Z. Zhang and S.C. Chang, "Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA," Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), January 2008.
21. Y.C. Lin and K.-T. Cheng, "Pseudo-Functional Scan-based BIST for Delay Fault," to appear in IEEE VLSI Test Symp. (VTS), May 2005.
22. Charles H.-P. Wen, L.-C. Wang, K.-T. Cheng, Kai Yang, and W.-T. Liu, "On A Software-Based Self-Test Methodology and Its Application," to appear in IEEE VLSI Test Symp. (VTS), May 2005.
23.
J.-C. Yeh,
Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, "Flash memory built-in self-diagnosis
withtest mode control," in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs,
May 2005 (to appear).
24.
C.-C. Wang,
J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu, "A BIST scheme for
FPGAinterconnect delay faults," in Proc. IEEE VLSI Test Symp. (VTS), Palm
Springs, May 2005(to appear).
25. C.-W. Wu, "SOC testing methodology and practice," in Proc. Design, Automation and Test in Europe (DATE), Munich, Mar. 2005 (to appear).
26. G. Parthasarathy, M. K. Iyer, K.-T. Cheng. "Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver," to appear in Proc. European Design and Test Conference (DATE), 2005.
27. J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman, Z. Zhang, "Instruction Set Extension with Shadow Registers for Configurable Processors, " to appear in Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, February 2005.
28. J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng, " Bitwidth-Aware Scheduling and Binding in High-Level Synthesis, " Proceedings of the Asia South Pacific Design Automation Conference, January 2005.
29.
D. Chen, J.
Cong, and J. Xu, "Optimal Module and Voltage Assignment for Low-Power, "
Proceedings of the
30.
J. Cong, M.
Romesis, and J. Shinnerl, " Fast Floorplanning by Look-Ahead Enabled
Recursive Bipartitioning, "; Proceedings of the
31. A. Jagannathan, H. Yang, K. Konigsfeld, D. Milliron, M. Mohan, M. Romesis, G. Reinman, and J. Cong, " Micro-Architecture Evaluation and Optimization with Interconnect Pipelining, " Proceedings of the Asia South Pacific Design Automation Conference, January 2005.
32. Y.-C Lin, L. Feng, K. Yang, and K.T. Cheng, "Constraints Extraction for Pseudo-Functional Scan-based Delay Testing," in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC'05), January 2005.
33.
C.-P. Su,
C.-L. Horng, C.-T. Huang, and C.-W. Wu, "A configurable AES processor for
enhanced security," in Proc. Asia and South Pacific Design Automation
Conf. (ASP-DAC), Shanghai, Jan. 2005.
34. C.-P. Su, C.-H. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "Design and test of a scalable security processor," in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Shanghai, Jan. 2005.
35. F. Lu, Madhu, Partha, Li and Cheng, "An Efficient Sequential SAT Solver With Improved Search Strategies," to appear in in Proc. European Design and Test Conference (DATE), 2005.
36. Kai Yang, Li-C. Wang, Kwang-Ting Cheng. "On Statistical Correlation Based Path Selection for Timing Validation" to appear in IEEE VLSI-TSA-DAT 2005.
37.
F. Lu, L.-C.
Wang, K.-T. Cheng, J. Moondanos and Z. Hanna. "A Signal Correlation Guided
Circuit-SAT Solver" to appear in Journal of Universal Computer Science.
38. C. Li, M. Xie, C.K. Koh, J. Cong, and P. Madden, "Routability-Driven Placement and White Space Allocation, " Proceedings of the International Conference on Computer-Aided Design, November 2004.
39. C.-T. Chao, L. Wang, K.-T. Cheng, and S. Kundu, "Static Statistical Timing Analysis for Latch-based Pipeline Designs," in Proc. of Int'l Conf. on CAD (ICCAD'04), Nov. 2004.
40. L Wang, J.-J. Liou and K.T. Cheng, "Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model," IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 23, No. 11, November 2004.
41. R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, "Fail pattern identi_cation for memory built-in self-repair," in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 366-371.
42. C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, and C.-W. Wu, "On test and diagnosticsof ash memories," in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov.2004, pp. 260-265.
43. H.-C. Hong, C.-W. Wu, and K.-T. Cheng, "A sigma-D modulation based analog BIST system with a wide bandwidth _fth-order analog response extractor for diagnosis purpose," in Proc.13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 62-67.
44. C.-L. Su, R.-F. Huang, C.-W. Wu, C.-C. Hung, M.-J. Kao, Y.-J. Chang, and W.-C. Wu, "MRAM defect analysis and fault modeling," in Proc. Int. Test Conf. (ITC), Charlotte, Oct.2004.
45.
K.-L. Cheng,
J.-R. Huang, C.-W. Wang, C.-Y. Lo, L.-M. Denq, C.-T. Huang, C.-W. Wu, S.-W.
Hung, and J.-Y. Lee, "An SOC test integration platform and its industrial
realization," in Proc. Int. Test Conf. (ITC), Charlotte, Oct. 2004.
46. Jianzhou Zhao, Jinian Bian, Weimin Wu, "PFGASAT-a Genetic SAT Solver Combining Partitioning and Fuzzy Strategies, " 28th COMPSAC'2004, Hong Kong, Sep. 2004, pp. 118-123.
47. G. Chen and J. Cong, "Simultaneous Timing Driven Clustering and Placement for FPGAs, "Proc. International Conference on Field Programmable Logic and its Applications, August 2004.
48.
Yang Changqi,
Hong Xianlong, Cai Yici, Jing Tong, Wu Weimin, "Data-Path Placement Based
on Regularity Extraction and Implementation, " Chinese Journal of
Semiconductors, vol. 25 No. 8, Aug. 2004, pp. 925-936
49. C.-H. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "A word-based RSA crypto-processor with enhanced pipeline performance," in Proc. 4th IEEE Asia-Paci_c Conf. Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Aug. 2004, pp. 218-221.
50. S.-F. Kuo, J.-C. Yeh, C.-W. Wu, and C.-H. Chen, "A systematic approach to semiconductor memory test time reduction," in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.
51. Y.-T. Lai, J.-C. Yeh, C.-W.Wu, and C.-H. Ho, "Flash memory built-in self-test with enhanced test mode control," in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.
52.
S.-H. Shieh
and C.-W. Wu, "A systematic approach to semiconductor memory test time
reduction," in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.
53.
L.-M. Denq,
R.-F. Huang,, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A parallel built-in
diagnostic scheme for multiple embedded memories," in Proc. IEEE Int.
Workshop on Memory Technology, Design and Testing (MTDT), San Jose, Aug. 2004,
pp. 65-69.
54. Y.-T. Chang and K.-T. Cheng, "Self-referential Verification for Gate-level Implementations of Arithmetic Circuits, " IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), July 2004.
55. J. Cong, Y. Fan, and Z. Zhang, " Architecture-Level Synthesis for Automatic Interconnect Pipelining, " Proceedings of the Design Automation Conference, June 2004, pp. 602 - 607.
56. L.-C. Wang, T.M. Mak, K.-T. Cheng and M.S. Abadir, "On Path-Based Learning and Its Applications In Delay Test And Diagnosis, " in Proc. Design Automation Conf., pp. 492-497, Jun. 7-11, 2004.
57. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan, "An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization, " ICCCAS'2004, Chengdu, June 2004, pp. 1276-1280.
58. S.C. Chang, J.D. Shieh, and K.C. Wu, "Re-synthesis for Delay Variation Tolerance, " Proc. IEEE/ACM Pro. Design Automation Conference, DAC, pp. 814-819, 2004.
59. Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu, "Module Placement Based on Quadratic Programming and Rectangle Packing Using Less Flexibility First Principle, " IEEE International Symposium on Circuits and Systems (ISCAS'2004), Vancouver, Canada, May 2004, pp. V61-V64.
60. Zhu Ming, Bian Jinian, Wu Weimin, "A Novel Collaborative Scheme of Simulation and Model Checking for Property Verification, " 8th CSCWD'2004, Xiamen, May 2004, pp. 67-72.
61. Changqi Yang, Xianlong Hong, Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu, "Recursively Combine Floorplan and Q-Place in Mixed Mode Placement Based on Circuit's Variety of Block Configuration, " IEEE International Symposium on Circuits and Systems (ISCAS'2004), Vancouver, Canada, May 2004, pp. V81-V84.
62. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu, "Stairway Compaction using Corner Block List and its Applications with Rectilinear Blocks, " ACM Trans. on Design Automation of Electronic System, Vol.9, No. 2, Apr 2004, pp. 199-211.
63.
R.-F. Huang,
C.-L. Su, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "\A memory built-in
self-diagnosis design with syndrome compression," in Proc. IEEE Int.
Workshop on Current & Defect Based Testing (DBT), Napa Valley, Apr. 2004,
pp. 97-102.
64. C.-K. Ong, D. Hong, K.-T. Cheng, and L.-C. Wang, "A Scalable On-Chip Jitter Extraction Technique," IEEE VLSI Test Symp. Apr 2004.
65. G. Parthasarathy, M. K. Iyer, K.-T. Cheng and L.-C. Wang, "Safety Property Verification Using Sequential SAT and Bounded Model Checking," IEEE Design and Test of Computers, Mar/Apr 2004.
66. C-K Ong, D Hong, K-T Cheng and L-C Wang, "Random Jitter Extraction for MultiI-Gigahertz Ssignals," European Design and Test Conference (DATE), March 2004.
67. M C-T Chao, L-C Wang and K-T Cheng, "Pattern Selection for Testing of Deep Sub-Micron Timing Defects," European Design and Test Conference (DATE), March 2004.
68. T Feng and L-C Wang, and K.-T. Cheng, "Improved Symbolic Simulation By Dynamic Functional Space Partitioning," European Design and Test Conference (DATE), March 2004.
69. J. Cong, Y. Fan, G. Han, and Z. Zhang, "Application-Specific Instruction Generation for Configurable Processor Architectures, " Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, February 2004.
70. D. Chen, J. Cong, F. Li, and L. He, "Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages, " Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, February 2004.
71. F. Li, Y. Lin, L. He, and J.Cong, "Low-power FPGA using Pre-Defined Dual-Vdd/Dual-Vt Fabrics, " Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, February 2004.
72.
M.-Y. Wang,
C.-P. Su, C.-T. Huang, and C.-W. Wu, "An HMAC processor with integrated
SHA-1 and MD5 algorithms," in Proc. Asia and South Pacific Design
Automation Conf. (ASP-DAC),
73.
R.-F. Huang,
Y.-T. Lai, Y.-F. Chou, and C.-W. Wu, "SRAM delay fault modeling and test
algorithm development," in Proc. Asia and South Pacific Design Automation
Conf. (ASP-DAC),
74. K. Yang, K.-T. Cheng, and L.-C. Wang, " TranGen: A SAT-Based ATPG for Path-Oriented Transition Fault, " in Proc. Asia and South Pacific Design Automation Conf., pp.92-97, Jan. 27-30, 2004.
75. C.K. Ong, D. Hong, K.-T. Cheng, and L.-C. Wang, "Jitter Spectral Extraction for Multi-gigahertz Signal, " in Proc. Asia and South Pacific Design Automation Conf., pp.298-303, Jan. 27-30, 2004.
76. C.-K. Ong, K.-T Cheng, L.-C. Wang, "A New SigmaDelta Modulator Architecture for Testing Using Digital Stimulus," In Proc Transaction of Circuits and Systems I: Fundamental Theory and Applications, January 2004.
77. G. Parthasarathy, M. K. Iyer, K.-T. Cheng and L.-C. Wang, "Efficient Reachability Checking using Sequential SAT, " in Proc. Asia and South Pacific Design Automation Conf., pp.418-423, Jan. 27-30, 2004.
78.
Jingjing Fu,
Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D Tan, "A Fast Decoupling
Capacitor Allocation Algorithm for Noise Reduction of Power Delivery Networks, "
IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2004),
Yokohama, Japan, Jan 2004, pp. 505-510.
79.
Jingyu Xu,
Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu, "A Coupling and Crosstalk
Considered Timing-Driven Global Routing Algorithm for High Performance Circuit
Design, " IEEE/ACM Asia & South Pacific Design Automation Conference
(ASP-DAC'2004), Yokohama, Japan, Jan 2004, pp. 677-682
80. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, et al., "Buffer Allocation Algorithm with Consideration of Routing Congestion, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2004), Yokohama, Japan, Jan 2004, pp. 621-623.
81. Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "A Buffer Planning Algorithm with Congestion Optimization, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2004), Yokohama, Japan, Jan 2004, pp. 615-620.
82. Liu Yang, Xiaobo Guo and Zeyi Wang, "An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2004), Yokohama, Japan, Jan 2004, pp. 702-706.
83. M.-Y. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "An HMAC processor with integratedSHA-1 and MD5 algorithms," in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 456-458.
84.
R.-F. Huang,
Y.-T. Lai, Y.-F. Chou, and C.-W. Wu, "SRAM delay fault modeling and
testalgorithm development," in Proc. Asia and South Pacific Design
Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 104-109.
85. S. Ghosh, K. W. Lai, W. B. Jone, S. C. Chang, "Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits, " ATS 2004.
86. C.T. Hsieh, J.C. Lin, and S.C. Chang, "A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits, " Proc. IEEE/ACM International Conference on Computer Aided Design, ICCAD, pp.537-540, 2004.
87. Tao Feng, Li-C.Wang, Kwang-Ting Cheng, Andy Lin, "Partitioned OBDD Data Structure in Verification," Proc. IEEE International High Level Design Validation and Test Workshop (HLDVT), 2004.
88. Wenjian Yu, Zeyi Wang and Xianlong Hong, "Preconditioned multi-zone boundary element analysis for fast 3D electric simulation, " Engineering Analysis with Boundary Elements, 2004, 28(9): 1035-1044.
89. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D, Zhu Pan, "A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Vhip Power Delivery, " IEICE Trans. Electron., Vol. E87-C, No.12, Dec 2004.
90. Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "A Buffer Planning Algorithm for Chip-Level Floorplanning," SCIENCE IN CHINA (Series F), Vol. 47, No. 6, pp. 763-776, 2004.
91. Heng Hu, Hong-Xi Xue and Ji-nian Bian, "HSM2 : A New Heuristic State Minimization Algorithm for Finite State Machine, " Journal of Computer Science and Technology, 2004, 19(5): 729-733.
92. Wang Y, Hong XL, Jing T, et al. "An efficient low-degree RMST algorithm for VLSI/ULSI physical design, " LECTURE NOTES IN COMPUTER SCIENCE 3254: 442-452, 2004.
93. Fu JJ, Luo ZY, Hong XL, Cai, YC, et al. "Simultaneous wire sizing and decoupling capacitance budgeting for robust on-chip power delivery, " LECTURE NOTES IN COMPUTER SCIENCE 3254: 433-441, 2004.
95.
Ming Zhu,
Jinian Bian, Weimin Wu, "Optimization Techniques in a Functional
Verification Platform for Embedded System, " Proc. ICESS'04, Hangzhou,
Dec. 2004, pp. 480-486, (will appear on LECTURE NOTES IN COMPUTER SCIENCE).
96.
Qiang Wu,
Jinian Bian, Hongxi Xue, "A Distributed Architecture Model for
Heterogeneous Multiprocessor System-on-Chip Design, " Proc. ICESS'04,
Hangzhou, Dec. 2004, pp. 124-130, (will appear on LECTURE NOTES IN COMPUTER
SCIENCE).
97.
Haili Wang,
Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang, "CA-Ex: A Tuning-Incremental
Methodology for Application-Specific Communication Architectures in Distributed
Embedded Systems, " Proc. ICESS'04, Hangzhou, Dec. 2004, pp. 7-14, (will
appear on LECTURE NOTES IN COMPUTER SCIENCE)
98.
Liu Yang,
Xiaobo Guo, Zeyi Wang, "An Approach to Solving the Linear Systems with
Multiple Right-Hand Side s in 3-D Parasitic Inductance Extraction," Acta
Electronica Sinica, Vol. 32 No. 11, 2004, pp. 1770-1773. (in Chinese)
99.
Zhuoyuan Li,
Weimin Wu, Xianlong Hong, "Incremental Placement Algorithm for Timing and
Routability Optimization, " Chinese Journal of Semiconductors, Vol.25
No.2, 2004, pp. 158-167.
100. Zhuoyuan Li, Weimin Wu, Xianlong Hong, "New Incremental Placement Algorithm Based on Integer Programming for Reducing Congestion, " Chinese Journal of Semiconductors, Vol.25 No.1, 2004, pp. 30-37.
101. Yongqiang Lu, Xianlong Hong, et al., "An Efficient Partitioning Method in Quadratic Placement, " Chinese Journal of Semiconductors, 2004, vol.25 No.3, pp. 272-278.
102.
Ling Zhang,
Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He. "CEE-Gr: A
Global Router with Performance Optimization under Multi-Constraints, "
Chinese Journal of Semiconductors, 2004, vol.25 No.5, pp. 508-515.
103.
Qiang Wu,
Jinian Bian, Xihong Xue, "ATMP:Multi-way Hardware-Software Partitioning Algorithm
Based on Abstract Architecture Template," Journal of Computer-aided Design
and Computer Graphics, Vol.16 No.11,2004, pp: 1562-1567. (in Chinese).
104.
Yawen Niu,
Qiang Wu, Jinian Bian, Hongxi Xue, "HCDFG-II-A Representation of Control/
Data Flow Graph for C Language System Specification," Journal of
Computer-aided Design and Computer Graphics, Vol.16 No.11, 2004, pp:1547-1552.
(in Chinese)
105. Qi Cai, Qiang Zhou, Tong Jing, Xianlong Hong, "XML-Based Middle Data Denotation in VLSI Physical Design VLSI, " Computer Engineering and Applications, Vol.34 No.40, 2004, pp:41-44. (in Chinese).
106. Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu. "UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing, " IEEE Trans. on CAD, 2004, 23(3): 358-365.
107. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu and Wayne Dai, "Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques, " IEEE Trans. on CAD, 2004, 23(7): 1086-1094.
108. Z. Ge, J. Liao and W.F. Wong, "Compiling to FPGAs via an EPIC Compiler's Intermediate Representation," To appear as poster in the IEEE International Conference on Field-Programmable Technology (FPT'03). Tokyo, Japan . Dec 2003.
109. C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, "A high-throughput low-cost AES processor," IEEE Communications Magazine, vol. 41, no. 12, Dec. 2003.
110. S.-H. Shieh and C.-W. Wu, "Asymmetric high-radix signed-digit number systems for carry-free addition," J. Inform. Science and Engineering, vol. 19, no. 6, Nov. 2003.
111. K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, "FAME: a fault-pattern based memory failure analysis framework," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2003 (to appear).
112. R.-F. Huang, Y.-F. Chou, and C.-W. Wu, "Defect oriented fault analysis for SRAM," in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003.
113. C.-L. Su, R.-F. Huang, and C.-W. Wu, "A processor-based built-in self-repair design for embedded memories," in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003.
114. Dong Sheqin, Hong Xianlong, Wu Yuliang, Gu Jun, A Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle, Journal of Computer Science and Technology, Vol.18, No.6, November 2003.
115. J. Cong, M. Romesis, and M. Xie "Optimality and Stability Study of Timing-driven Placement Algorithms, " Proceedings of International Conference on Computer Aided Design, pp. 472-478, November 2003.
116. J. Cong, Y. Fan, G. Han X. Yang and Z. Zhang "Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication, " Proceedings of International Conference on Computer Aided Design,, pp. 536-543, November 2003.
117. Z. Zhang, Y. Fan, M. Potkonjak and J. Cong, "Gradual Relaxation Technique with Application to Behavioral Synthesis, " Proceedings of International Conference on Computer Aided Design,, pp. 529-535, November 2003.
118. T. F. Chan, J. Cong, J. Shinnerl and K. Sze, "An Enhanced Multilevel Algorithm for Circut Placement, " Proceedings of International Conference on Computer Aided Design,, pp. 299-306, November 2003.
119. J. Cong, T. Kong, J. Shinnerl, M. Xie and X. Yuan, "Large-Scale Circuit Placement: Gap and Promise, " Proceedings of International Conference on Computer Aided Design, pp. 883-890, November 2003.
120. Angela Krstic, Li-C Wang, Kwang-Ting Cheng, and T.M. Mak, "Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies" IEEE International Test Conference, October 2003.
121. Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "An O(nloglogn) algorithm for Evaluation of Bounded Slice-line Grid," In: Proceedings of IEEE ASICON, Beijing, China, 21-24 Oct. 2003.
122. Hongchuan Wei, Zeyi Wang, "A weighted average formula for efficient inductance and resistance extraction, " In: Proceedings of IEEE ASICON, Beijing, China, Oct. 2003, pp. 996-999.
123. Liu Yang, Zeyi Wang, "A 3-D fast extractor for interconnect inductance of multiple right-hand sides, " In: Proceedings of IEEE ASICON, Beijing, China, Oct. 2003, pp. 988-991.
124. Xiren Wang, Wenjian Yu, Deyan Liu, Zeyi Wang, "Fast extraction of 3-D interconnect resistance: numerical-analytical coupling method, " In: Proceedings of IEEE ASICON, Beijing, China, Oct. 2003, pp. 315-318.
125. Wenjian Yu, Zeyi Wang, "A new approach to selecting the cutting number in QMM-based capacitance extraction, " In: Proceedings of IEEE ASICON, Beijing, China, Oct. 2003, pp. 980-983.
126. Wenjian Yu, Zeyi Wang, "Enhanced QMM-BEM solver for 3-D finite-domain capacitance extraction with multilayered dielectrics, " Proc. International Conference on Computer Design 2003, San Jose, USA, Oct. 2003, pp. 58-63.
127.
Yang Xiao,
Yufeng Wang, Jinian Bian, "Placement-Aware Retiming and Rescheduling in
High-Level Synthesis, " CAID&CD'2003, Hangzhou, Oct. 2003, pp. 556-561.
128. H.-C. Hong, J.-L Huang, K.-T. Cheng, C.-W. Wu, and D.-M. Kwai, "Practical considerations in applying - modulation-based analog bist to sampled-data systems," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, Sept. 2003.
129. C.-W. Wang, K.-L. Cheng, J.-N. Lee, Y.-F. Chou, C.-T. Huang, C.-W. Wu, F. Huang, and H.-T. Yang, "Fault pattern oriented defect diagnosis for memories," in Proc. Int. Test Conf. (ITC), Charlotte, Sept. 2003, pp. 29-38.
130. J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow, "A built-in self-repair scheme for semiconductor memories with 2-D redundancy," in Proc. Int. Test Conf. (ITC), Charlotte, Sept. 2003, pp. 393-402.
131. J. Liao, W.F. Wong, and M. Tulika, "A Model for Hardware Realization of Kernel Loops," Proc. of 13th International Conference on Field Programmable Logic and Application, Lecture Notes of Computer Science, vol. 2778, pp. 334-344. Springer-Verlag. Sep 2003.
132. Yongqiang Lu, Xianlong Hong, Changqi Yang, Wenting Hou, Yuchun Ma, " An Efficient Partitioning Method for Very Large-scale Standard Cell Placement with Pre-designed Macros," In: Proceedings of IEEE ASICON, Beijing, China, 2003, Volume 1, pages 270-273, Sept. 2003.
133. Liu Yang, Xianlong Hong, Yici Cai, Qiang Zhou, Changxu Du, "A Multi-layer Area Routing Algorithm with Optimized Pin Mapping Strategy, " ASICON'2003, Beijing, pp. 229-232, Sep. 2003.
134. Zhuoyuan Li, Weimin Wu, Xianlong Hong, "Incremental Placement Algorithm for Multi-objective Optimization," ASICON'2003, Beijing, pp. 178-182, Sep. 2003.
135.
Yongqiang Lu,
Xianlong Hong, Changqi Yang, Wenting Hou, Yuchun Ma, "An Efficient
Partitioning Method for Very Large-scale Standard Cell Placement with
Pre-designed Macros, " ASICON'2003, Beijing, pp. 270-273, Sep. 2003.
136. Changqi Yang, Xianlong Hong, Yici Cai, Wenting Hou, et al., "Standard-Cell Based Data-Path Placement Utilizing Regularity, " ASICON'2003, Beijing, pp. 97-100, Sep. 2003.
137.
Jingyu
Xu, Xianlong Hong, Tong Jing, Ling Zhang, "ETEM: An Efficient Gate and
Interconnect Timing Estimator Considering Cross-Coupling for High Performance
Layout, " ASICON'2003, Beijing, pp. 254-257, Sep. 2003.
138.
Yang Yang, Qi
Zhu, Tong Jing, Xianlong Hong, Yin Wang, "Rectilinear Steiner Minimal Tree
among Obstacles, " ASICON'2003, Beijing, pp. 348-351, Sep. 2003.
139.
Song Chen, X.
Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "An O(nloglogn) algorithm
for Evaluation of Bounded Slice-line Grid," ASICON'2003, Beijing, pp.
208-211, Sep. 2003.
140. Tong Jing, Xianlong Hong, "The Key Technologies of Performance Optimization for Nanometer Routing, " ASICON'2003, Beijing, pp. 118-123, Sep. 2003. (Invited Paper).
141.
Ling
Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He, "Performance
Optimization Global Routing with RLC Crosstalk Constraints, " ASICON'2003,
Beijing, pp. 191-194, Sep. 2003. (Outstanding Student Paper Award)
142.
Qiang Wu,
Jinian Bian, Hongxi Xue, Yiping Fan, Weimin Wu, Xianlong Hong and Jun Gu, "Applying
Search Space Smoothing Technique to Hardware/Software Partitioning, "
ASICON'2003, Beijing, pp. 85-88, Sep. 2003.
143. Hu Heng, Hongxi Xue, Jinian Bian, "A heuristic state assignment algorithm targeting area, " ASICON'2003, Beijing, pp. 93-96, Sep. 2003.
144. Wang Yunfeng, Bian Jinian, Wu Qiang, Hu Heng, "Reallocation and Rescheduling after Floor-planning for Timing Optimization, " ASICON'2003, Beijing, pp. 212-215, Sep. 2003.
145. Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue, "Property-Classified Hybrid Verification based on CDFG, " ASICON'2003, Beijing, pp. 233-237, Sep. 2003.
146. Jingjing Fu, Xianlong Hong, Yici Cai, Zuying Luo, "Decoupling Capacitor Allocation for Power Delivery Network Noise Reduction Based on Standard Cell Layouts, " ASICON'2003, Beijing, pp. 101-104, Sep. 2003.
147. D. Chen, J. Cong, and Y. Fan, "Low-Power High-Level Synthesis for FPGA Architectures, " 2003 International Symposium on Low Power Electronics and Design, Seoul, Korea, pp. 134 - 139, Aug. 2003.
148. L.-M. Denq, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A parallel built-in self-diagnosis scheme for embedded memory," in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 449-452.
149. H.-C. Liao, R.-F. Huang, J.-J. Liou, and C.-W. Wu, "An FPGA fault simulator for stuck-at and segment delay faults," in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 461-464.
150. S.-H. Shieh, C.-K. Tung, L.-R. Wu, and C.-W. Wu, "Low-power full adder core design for embedded structure," in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 221-224.
151. S.-H. Shieh and C.-W. Wu, "Carry-free adder design based on minimal redundant positive-digit number system," in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 257-260.
152. J.-H. Hong, C.-L. Liu, B.-Y. Tsai, and C.-W. Wu, "A radix-4 modular multiplier for fast RSA public-key cryptosystem," in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 553-556.
153. H.-C. Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang,, and S.-K. Lu, "Efficient double fault diagnosis for CMOS logic circuits with a specific application to generic bridging faults," J. Inform. Science and Engineering, vol. 19, no. 4, pp. 571-587, July 2003.
154. M.-C. Sun, C.-P. Su, C.-T. Huang, and C.-W. Wu, "Design of a scalable RSA and ECC crypto-processor," in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 495-498, (Best Pad C.-W. Wu, "A testability-driven optimizer and wrapper generator for embedded memories," in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, July 2003, pp. 53-56.
155.
Qiang Zhou,
Qi Cai, Xianlong Hong, Yici Cai, "Design and Implementation of VLSI
Physical Design Data Markup Language-PhyD-XML," Journal of Computer-aided
Design and Computer Graphics, Vol.15 No.17, July 2003, pp: 773-777 (in Chinese)
156. J. Cong, A. Jagannathan, G. Reinman and M. Romesis, "Microarchitecture Evaluation with Physical Planning, " ACM/SIGDA Proceedings of the 40th Design Automation Conference, Anaheim, California, pp. 32 - 35, June 2003.
157. Jing-Jia Liou, Angela Krstic, Yi-Ming Jiang, and Kwang-Ting Cheng, "Modeling, Testing, and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 22, No. 6, pp. 756-769, June 2003.
158. Chee-Kian Ong, Kwang-Ting (Tim) Cheng, and Li-C Wang, "Delta-sigma Modulator Based Mixed-signal BIST Architecture for SoC, " IEEE International Mixed-Signal Testing Workshop (IMSTW), June 2003.
159. C.-K. Ong, P.-W. Luo, Y.-J. Chang, K.-T. Cheng, and W.-C. Wu, "DfT Sigma-Delta Modulator Architecture Implementation," IEEE International Mixed-Signal Testing Workshop (IMSTW), June 2003.
160. A. Krstic, L.-C. Wang, K.-T. Cheng, J.-J. Liou, and T.M. Mak, "Enhancing Diagnosis Resolution for Delay Defects Based Upon Statistical Timing and Statistical Fault Models, " Proceedings of ACM/ IEEE Design Automation Conference, pp. 668-673, June 2003.
161. Feng Lu, Li-C Wang, K.-T. Cheng, John Moondanos, and Ziyad Hanna, "A Signal Correlation Guided ATPG Solver and Its Applications For Solving Difficult Industrial Cases," ACM/IEEE Design Automation Conference, pp. 436-441, June 2003.
162. J.-H. Hong and C.-W. Wu, "Cellular array modular multiplier for the RSA public-key cryptosystem based on modified Booth's algorithm," IEEE Trans. VLSI Systems, vol. 11, no. 3, pp. 474-484, June 2003.
163. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, et al., "Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis, " IEEE/ACM Design Automation Conference (DAC'2003), USA, June 2003, pp. 806-811.
164. Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "Evaluating a bounded slice-line grid assignment in O(nlogn) time" ISCAS'03. Proceedings of the 2003 International Symposium on, Volume: 4, Thailand, May 25 - 28, 2003 Page(s): 708 -711.
165. Wenjian Yu, Zeyi Wang, "Enhanced quasi-multiple medium technology for fast finite-domain electrostatic BEM simulation, " Proc. 15th International Conference on Boundary Element Technology, Detroit, USA, May 2003, pp. 65-74.
166.
Yongqiang Lu,
Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai, "Combining Clustering and
Partitioning in Quadratic Placement, " IEEE International Symposium on
Circuits and Systems (ISCAS'2003), Bangkok, Thailand, May 2003, pp. IV720-IV723
167. Angela Krstic, Li-C Wang, Kwang-Ting Cheng, and J-J Liou, "Diagnosis of Delay Defects Using Statistical Timing Models, " Proceedings of 21st IEEE VLSI Test Symposium (VTS'03), April 2003.
168. Kaushik Roy, T. M. Mak, and Kwang-Ting Cheng, "Test Consideration for Nanometer Scale CMOS Circuits, " Proceedings of 21st IEEE VLSI Test Symposium, (VTS'03), April 2003.
169. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Testing and diagnosis methodologies for embedded content addressable memories," J. Electronic Testing: Theory and Application, vol. 19, no. 2, pp. 207-215, Apr. 2003.
170. J. Cong, Y. Fan, X. Yang and Z. Zhang, "Architecture and Synthesis for Multi-Cycle Communication, " ACM/SIGDA Proceedings of 2003 International Symposium on Physical Design,pp. 190-196, Monterey, California, April 2003.
171. J. Cong, M. Romesis and M. Xie, "Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms, " Proceedings of the International Symposium on Physical Design, Monterey, California, pp. 88 - 94, April 2003.
172. Sheqin Dong, Xianlong Hong, Rectangle-packing-based floorplanning algorithms for system-on-a-chip design, Qinghua Daxue Xuebao, Vol.43, No.4, Apr. 2003, p484-486.
173.
Yuchun Ma,
Xianlong Hong, Sheqin Dong, Song Chen, et al., "An Integrated
Floorplanning with an Efficient Buffer Planning Algorithm, " ACM
International Symposium on Physical Design (ISPD'2003), USA, April 2003, pp.
136-142.
174. MingHung Lee, TingTing Hwang, "Decomposition of Extended Finite State Machine for Low Power Design, " Proc. of DATE-2003, pp. 1152-1153, Germany, March 2003.
175. Y. L. Lo, Allen C. H. Wu and TingTing Hwang, "A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Design, " Proc. of DATE-2003, pp. 1102-1103, Germany, March 2003.
176. C. Y. Chang, Allen C. H. Wu and TingTing Hwang, "G-MAC:An Application-Specific MAC/Co-Processor Synthesizer, " Proc. of DATE-2003, pp. 1134-1135, Germany, March 2003.
177. Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, and Li-C Wang, "On Structural vs. Functional Testing for Delay Faults, " Proceedings of IEEE International Symposium on Quality Electronic Design, March 2003.
178. Angela Krstic, Li-C Wang, Kwang-Ting Cheng, Jing-Jia Liou, and Magdy S. Abadir, "Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step, " Proceedings of Design Automation and Test in Europe (DATE), March 2003 (Best Paper Award).
179. Feng Lu, Li-C Wang, Kwang-Ting Cheng, Ric C-Y Huang, "A Circuit SAT Solver with Signal Correlation Guided Learning," Proceedings of Design Automation and Test in Europe (DATE), March 2003.
180. J. Y. Lin, A. Jagannathan and J. Cong, "Placement-Driven Technology Mapping For LUT-Based FPGAs, " ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 121 - 126, February 2003.
181. F. Li, D. Chen, L. He, and J. Cong, "Architecture Evaluation for Power-Efficient FPGAs, " ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 175 - 184, February 2003.
182. Chee-Kian Ong, Kwang-Ting (Tim) Cheng, and Li-C Wang, "Delta-Sigma Modulator Based Mixed-Signal BIST Architecture for SoC," Proceedings of Asia and South Pacific Design Automation Conference, pp. 669-674, January 2003.
183. Jing-Jia Liou, Li-C Wang, Angela Krstic, and Kwang-Ting Cheng, "Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation, " Proceedings of AM/ IEEE ASP Design Automation Conference, pp. 751-756, January 2003.
184. Tao Feng, Li-C Wang, Kwang-Ting Cheng, Manish Pandey, and Magdy S. Abadir, "Enhanced Symbolic Simulation For Efficient Verification of Embedded Array Systems," Proceedings of ACM/IEEE Design Automation Conference, pp. 302-307, January 2003.
185. Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "Buffer Planning Algorithm Based on Dead Space Redistribution," Proceeding, ASP-DAC Kitakyushu, Japan, Jan. 21-24 2003, p435-438.
186. Taotao Lu, Zeyi Wang and Xianlong Hong, "BBE: Hierarchical Computation of 3-D Interconnect Capacitance with BEM Block Extraction, " ASP-DAC 2003, pp. 255-260, Japan, Jan. 2003.
187. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, et al., "A buffer planning algorithm based on dead space redistribution, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2003), Kitakyushu, Japan, Jan 2003, pp. 435-438.
188. Tong Jing, Xian-Long Hong, Hai-Yun Bao, Yi-Ci Cai, Jing-Yu Xu, Chung-Kuan Cheng, Jun Gu, "UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2003), Kitakyushu, Japan, Jan 2003, pp. 834-839.
189. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu, "A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2003), Kitakyushu, Japan, Jan 2003, pp. 847-850.
190. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai, "A Path-based Timing-driven Quadratic Placement Algorithm, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2003), Kitakyushu, Japan, Jan 2003, pp. 745-748.
191. Zhuoyuan Li, Weimin Wu, Xianlong Hong, "Congestion Driven Incremental Placement Algorithm for Standard Cell Layout, " IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC'2003), Kitakyushu, Japan, Jan 2003, pp. 723-728
192. C.-C. Chang, J. Cong and Y. Xin, "Multi-level Placement for Large-Scale Mixed-Size Designs," Asia South Pacific Design Automation Conference, Kitakyushu, Japan, January 2003.
193. J. Cong, Y. Fan, G. Han and Z. Zhang, "Architecture and synthesis for multi-cycle on-chip communication, " Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis, Newport Beach, CA, 2003.
194. Zhan Xu, Xiaolang Yan, Yongjiang Lu, Haitong Ge, "Equivalence Checking Using Independent Cuts," Proceedings of the 12th Asian Test Symposium(ATS 2003).
195. Xiaolang Yan, Ye Chen, Zheng Shi, Zhijin Chen "Architecture of a Post-OPC Silicon Verification Tool," Proceedings of the 5th International Conference On ASIC (ASICON 2003).
196. Li Xing, Yan Xiao-lang, Ge Hai-tong "Approaches of Error Diagnosis and Correction in Combinational Circuits," Proceedings of the 5th International Conference on ASIC (ASICON 2003).
197. Yang Xiao, Yufeng Wang, Jinian Bian, "Layout-Aware Retiming and Rescheduling in High-Level Synthesis, " The 5th International Conference on Computer Aided Industrial Design and Conceptual Design, (CAID/CD03), 2003, Hangzhou 556-561.
198. Jinian Bian, Hongxi Xue, Zhengsheng XU, Lingjun Xu, Yunfeng Wang, Yu-Liang Wu, "Local Logic Substitution Algorithm for Post-Layout Re-synthesis, " The 5th International Conference on ASIC (ASICON03), 2003, Beijing 136-139 Qiang Wu, Jinian Bian, Hongxi Xue, Yiping Fan, Weimin Wu, Xianlong Hong and Jun Gu, "Applying Search Space Smoothing Technique to Hardware/Software Partitioning, " The 5th International Conference on ASIC (ASICON03), 2003, Beijing 85-88.
199. Wang Yunfeng, Bian Jinian, Wu Qiang, Hu Heng Re-synthesis after Floor-planning for Timing Optimization, "The 5th International Conference on ASIC (ASICON03), 2003, Beijing 212-215 Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue Property-Classified Hybrid Verification based on CDFG The 5th International Conference on ASIC (ASICON03), 2003, Beijing 233-237.
200. Hu Heng, Hongxi Xue, Jinian Bian, "A heuristic state assignment algorithm targeting area, " The 5th International Conference on ASIC (ASICON03), 2003, Beijing 93-96.
201. Jin Chen, Qiang Wu, Jinian Bian, Hongxi Xue, "SGA - A Self-adaptable granularity Approach for Hardware/Software Co-design, " The 5th International Conference on ASIC (ASICON03), 2003, Beijing 365-368.
202. Haili Wang, Qiang Wu, Jinian Bian, Zhihui Xiong, Jihua Chen, Sikun Li, "A Novel Virtual-Real Component Synthesis Approach in SoC Design, " The 8th International Conference on Computer Aided Design and Computer Graphics (CAD/Graphics03), 2003, Macau 151-156.
203. Qiang Wu, Yunfeng Wang, Jinian Bian, Hongxi Xue, "Graph Transformations on CDFG for Granularity Selection in Hardware-Software Partitioning, " The 8th International Conference on Computer Aided Design and Computer Graphics (CAD/Graphics03), 2003, Macau 303-308.
204. Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue, "Property Classification for Functional Verification based on CDFG (short), " The 12th Asian Test Symposium (ATS03), 2003.
205. Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue, "Property Classification for Hybrid Verification, " The 4th Workshop on RTL and High Level Testing (WRTLT03), 2003, Xian 129-132.
206. Jianzhou Zhao, Jinian Bian, Weimin Wu, "ACSAT: A SAT Solver via Solving TSP by ACO, "The 4th Workshop on RTL and High Level Testing (WRTLT03), 2003, Xian 133-137 Weimin Wu, Di Wang, Weiwei Zheng, Jinian Bian, Ming Zhu, "Safety Checking by Problem Solving, "The 4th Workshop on RTL and High Level Testing (WRTLT03), "2003, Xian 151-156.
207. Di Wang, Tao Liu, Weimin Wu, Xianlong Hong, "Prototype for Automatic Layout Modification in Alternating Phase-Shift Mask, " The 5th International Conference on Computer Aided Industrial Design and Conceptual Design, (CAID/CD03), 2003, Hangzhou 272-276.
208. Weimin Wu, Di Wang, Weiwei Zheng, Jinian Bian, Ming Zhu, " Property Checking Using RTL ATPG, " The 5th International Conference on Computer Aided Industrial Design and Conceptual Design, (CAID/CD03), 2003, Hangzhou 871-875.
209. Zhuoyuan Li, Weimin Wu, Xianlong Hong, "Congestion Driven Incremental Placement Algorithm for Standard Cell Layout, " ACM/IEEE Asia and Pacific Design Automation Conference, (ASPDAC03), 2003, 723-728.
210. Zhuuoyuan Li, Weimin Wu, Yang Wang, Xianlong Hong, "An Efficient Approach to Rule-Based Optical Proximity Correction, " Chinese Journal of Semiconductors, Vol.24, N0.12, 2003.
211. Di Wang, Weimin Wu, Zhuoyuan Li Xianlong Hong, "An Efficient Search Space Smoothing Based Netlist Partitioning, " The 5th International Conference on ASIC (ASICON03), 2003, Beijing 274-277.
212. Zhuoyuan Li, Weimin Wu, Xianlong Hong, "Incremental Placement Algorithm for Wirelength and Congestion Optimization, " Chinese Journal of CAD/CG, vol5, No.6, 2003, 651-655.
213. Zhuuoyuan Li, Weimin Wu, Xianlong Hong, Yang Wang, "Rule-Based Optical Proximity Correction with v-Support Vector Regression, " The 8th International Conference on Computer Aided Design and Computer Graphics (CAD/Graphics03), 2003, Macau 151-156.
214. Weimin Wu, Zhuoyuan Li, Hanbin Zhou, Xianlong Hong, Jinian Bian, "A Size-Balancing Approach to Mixed Mode Placement, " The 8th International Conference on Computer Aided Design and Computer Graphics (CAD/Graphics03), 2003, Macau 309-314.
215. C.-P. Su and C.-W. Wu, "A graph-based approach to power-constrained SOC test scheduling," J. Electronic Testing: Theory and Application, accepted 2003.
216. C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, "Built-in redundancy analysis for memory yield improvement," IEEE Trans. Reliability, 2003.
217. H.-C. Hong and C.-W. Wu, "Selection of high-order analog response extractor for - modulation based analog built-in self-test applications," J. Chinese Institute of Electrical Engineering, 2003.
218. B.-H. Lin, C.-W. Wu, and A. Luh, "Efficient and economic test equipment setup by pro-correlation," IEEE Design & Test of Computers, 2003.
219. Zhaozhi Yang, Zeyi Wang, "A virtual 3-D fast extractor for interconnect capacitance of multiple dielectrics, " Microelectronic Engineering, Vol. 65, pp. 133-144, 2003.
220. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu. "A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design, " IEICE Trans. on Fundamentals of ECCS, 2003, E86-A(12): 3158-3167.
221. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai, "FaSa: A Fast and Stable Quadratic Placement Algorithm," Journal of Computer Science and Technology, 2003, 18(3): 318-324.
222. Tong Jing, Xian-Long Hong, Hai-Yun Bao, Jing-Yu Xu, Jun Gu. "SSTT: Efficient Local Search for GSI Global Routing, " Journal of Computer Science and Technology, 2003, 18(5): 632-640.
223. Xian-Long Hong, Tong Jing, Jing-Yu Xu, Hai-Yun Bao, Jun Gu. "CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing, " Journal of Computer Science and Technology, 2003, 18(6): 732-738.
224. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, et al., "Evaluating a bounded slice-line grid assignment in O(nlogn) time, " IEEE International Symposium on Circuits and Systems (ISCAS'2003), Bangkok, Thailand, May 2003, pp. IV708-IV711.
225. Yuchun Ma, Xianlong Hong, Sheqin Dong, et al., "Arbitrary Convex and Concave Rectilinear Block Packing based on Corner Block List, " IEEE International Symposium on Circuits and Systems (ISCAS'2003), Bangkok, Thailand, May 2003, pp. V493-V496.
226. Xianlong Hong, Qi Zhu, Tong Jing, Yin Wang, Yang Yang, Yici Cai, Non-Rectilinear On-Chip Interconnect--An Efficient Routing Solution with High Performance, Chinese Journal of Semiconductors, Vol. 24 No. 3, 2003, pp: 225-233.(in Chinese).
227.
Zhuoyuan Li,
Weimin Wu, Xianlong Hong, "Incremental Placement Algorithm for Wirelength
and Routability Optimization," Journal of Computer-aided Design and Computer
Graphics, Vol.15, No.6, June 2003, pp: 652-655 (in Chinese)
228.
Changqi Yang,
Xianlong Hong, Weimin Wu, Yici Cai, "An Object-Based Approach to Optical
Proximity Correction," Journal of Computer-aided Design and Computer
Graphics, Vol.15 No. 3, 2003, pp255 - 258. (in Chinese)
229.
Tao Li, Zeyi
Wang, "2-D Interconnect Inductance and Resistance Extraction Based on the
Coupled Circuit Method," Journal of Computer-aided Design and Computer
Graphics, Vol.15 No.1, 2003, pp. 102-106. (in Chinese).
230.
Yu Hu, Tong
Jing, Xianlong Hong, Qiang Zhou, Ming Shen, "Data Management for Data-Path
Layout System," MICROELECTRONICS, Vol. 33, No.4 2003, pp: 301-305. (in
Chinese)
231.
Ling
Zhang, Tong Jing, Xianlong Hong, Changqi Yang, Ming Shen, "GUI Design
Based on Registration Mechanism for Data-Path Layout, " Computer
Engineering and Applications, Vol. 30 No.9, 2003, pp:127-129.(in Chinese)
232. Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, and Cheng-Wen Wu, "On-chip analog response extraction with one-bit delta-sigma modulators," IEEE Asian Test Symp., Nov. 2002.
233. Jing-Jia Liou, Li-C Wang, and Kwang-Ting Cheng, "On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing," Proceedings of ICCAD Conference, pp. 94-100, November 2002.
234. C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "Test scheduling of BISTed memory cores for SOC," in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002.
235. J. Cong, M. Xie and Y. Zhang, "An Enhanced Multilevel Routing System, " Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp 51-58, November 2002.
236. Jing-Jia Liou, Li-C Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, and Thomas W. Williams, "Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme," Proceedings of IEEE International Test Conference, pp. 407-416, October 2002.
237. Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C Wang, Kwang-Ting Cheng, and Magdy S. Abadir, "Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems," Proceedings of IEEE International Test Conference, pp. 203-212,October 2002.
238. C.K. Ong, J. L. Huang, and K.-T. Cheng, "Testing Second-Order Delta-Sigma Modulators Using Pseudo-Random Patterns, " Microelectronics Journal, Vol. 33, No 10, pp. 807-814 October 2002.
239. Y.-T. Lin, C.-P. Su, C.-T. Huang, C.-W. Wu, S.-Y. Huang, and T.-Y. Chang, "Low-power embedded memory architecture design for SOC," in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 306-309.
240. Yi-Ping You, Ching-Ren Lee and Jenq Huen Lee, "Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors, " LCPC (Languages and Compilers for High-Performance Computing), Maryland, July 2002.
241. Young-Jia Lin, Yuan-Shin Hwang and Jenq Kuen Lee, "Compiler Optimizations with DSP-Specific Semantic Descriptions, " LCPC (Languages and Compilers for High-Performance Computing, Maryland), July 2002.
242. R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, "A simulator for evaluating redundancy analysis algorithms of repairable embedded memories," in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Isle of Bendor, France, July 2002, pp. 68-73.
243.
Zhu Ming,
Bian Jinian, Xue Hongxi, "Uniform Internal Model for Hybrid Language
Description, " ICCCAS'2002, Chengdu, June 2002, pp. 1322-1325
245. Qiang Wu, Yunfeng Wang, Jinian Bian, Weimin Wu, Hongxi Xue, "A Hierarchical CDFG as Intermediate Representation for Hardware/Software Codesign, " ICCCAS'2002, Chengdu, June 2002, pp. 1429-1432.
246. Ying-Tsai Chang and Kwang-Ting (Tim) Cheng, "Self-referential verification of gate-level implementations of arithmetic circuits," Proceedings of 39th Design Automation Conference, June 2002.
247. Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, C.K. Cheng and Jun Gu, "Corner Block List Representation and CBL based Floorplanning Algorithm with Boundary Constraints, " Science In China (Series E), Vol. 32 No. 3,pp.409-418 June 2002.
248. Sheqin Dong, Xianlong Hong, Shuo Zhou and Jun Gu, "Efficient VLSI Module Placement with Solution Space Smoothing, " ICCCAS2002, Chengdu, June 2002.
249. Rui Liu, Xianlong Hong, Sheqin Dong, Yici Cai and Jun Gu, " Module Placement with Boundary Constraints Using O-Tree Representation, " IEEE International Symposium on Circuits and Systems (ISCAS2002), Scottsdale, Arizona, May 2002.
250. Tong Jing, Xianlong Hong, "A Novel And Efficient Timing-Driven Global Router For Standard Cell Layout Design Based On Critical Network Concept, " IEEE International Symposium on Circuits and Systems (ISCAS2002), Scottsdale, Arizona, USA, May 2002.
251. C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "A test access control and test integration system for system-on-chip," in Sixth IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Monterey, California, May 2002, pp. P2.1-P2.8.
253. M. K. Iyer, K.-T. Cheng, "Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs," VLSI Test Symposium, April, 2002.
254. Ki-Wook Kim, TingTing Hwang, C. L. Liu and Sung-Mo Kang, "Logic Transformation for Low Power Synthesis, " ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 2, pp 265-283, April 2002.
255. C.-P. Su and C.-W. Wu, "Graph-based power-constrained test scheduling for SOC," in Proc. IEEE Int. Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Brno, Czech Republic, Apr. 2002, pp. 61-68, (Best Paper Award).
256. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Testing and diagnosing embedded content addressable memories," in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 389-394.
257. K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, "RAMSES-FT: A fault simulator for flash memory testing and diagnostics," in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 281-286.
258. J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "A hierarchical test scheme for system-on-chip designs," in Proc. Design, Automation and Test in Europe (DATE), Paris, Mar. 2002, pp. 486-490.
259. Yuchun Ma, Xianlong Hong, Sheqing Dong, Yici Cai, C.K. Cheng and Jun Gu, "Stairway Compaction using Corner Block List and Its Applications with rectilinear blocks, " Proceedings of 7th IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC2002), Bangalore, India, January 2002.
260. Shuzhou Fang, Zeyi Wang and Xianlong Hong, "A 3-D Minimum-order Boundary Integral Equation Technique to Extract Frequency-dependent Inductance and Resistance in ULSI, " Proceedings of 7th IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC2002), Bangalore, India, January 2002.
261. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai and Jun Gu, "An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing, " Proceedings of 7th IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC2002), Bangalore, India, January 2002.
262. J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, " Flash memory built-in self-test using march-like algorithms," in Proc. IEEE Int. Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, Jan. 2002, pp. 137-141.
263. Zhong Chen, Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang, "Pilot - A Platform-Based HW/SW Synthesis System for FPSoC," submitted to Workshop on Software Support for Reconfigurable Systems.
264. Shih-Liang CheRefen, TingTing Hwang, and C. L. Liu, "A Technology Mapping Algorithm for CPLD Architectures, " Proc. of IEEE International Conference on Field Programmable Technology, 2002.
265. ChiTa Wu and TingTing Hwang, "Instruction Buffering for Nested Loop in Low Power Design, " Proc. of ISCAS'02, Scottsdale, Arizona, pp. IV81-IV84 2002.
266. Jerry C.-Y. Kao, Ching-Feng Su and Allen C.-H. Wu, "High-Performance FIR Generation Based on A Timing Driven Architecture and Component Selection Method, " IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 2002.
267. Irene M.-J. Liao, Ching-Feng Su, Alex C.-Y. Chang and Allen C.-H. Wu, "A Carry-Select-Adder Optimization Technique for High-Performance Booth-Encoded Wallace-Tree Multipliers, " IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 2002.
268. Shih-Liang Chen, TingTing Hwang, and C. L. Liu, "A Technology Mapping Algorithm for CPLD Architectures, " Proc. of IEEE International Conference on Field Programmable Technology, pp. 204-210, Hong Kong, 2002.
269. Cin-Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian, "Accelerating Logic Rewriting Using Implication Analysis, " IEICE Transactions on Fundamentials of Electronics, Communications and Computer Sciences, E85-A(12), 2002.12 2725-2736.
270. T. K. Tien, S.C. Chang and T.K. Tsai, "Crosstalk Alleviation for Dynamic PLAs, " Proc. IEEE/ACM Design, Automation and Test in Europe DATE, pp. 683-687, 2002.
271. T. K. Tien, C.C. Hsu, Y.Y. Liu and S.C. Chang, "Timing Optimization for Dynamic PLAs by Reordering Lines, " 13th VLSI/CAD symposium 2002.
272. Fang Shuzhou and Wang Zeyi, "A minimum-order boundary element method to extract the 3-D inductance and resistance of the interconnects in VLSI, " SCIENCE IN CHINA (Series F), Vol. 45, No. 6, pp. 453-461, 2002.
273. Liu Yang, Zeyi Wang, "A 3-D Fast Inductance and Resistance Extractor for Interconnects," Acta Electronica Sinica, Vol. 30 No. 11, 2002, pp. 1593-1596. (in Chinese).
274. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu, " VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation, " IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A, No. 11, pp.2697-2704, November 2001.
275. Parthasarathy, G.; Chung-Yang Huang; Kwang-Ting Cheng, "An analysis of ATPG and SAT algorithms for formal verification,". Proceedings Sixth IEEE International High-Level Design Validation and Test Workshop, Nov. 2001. p.177-82.
276. Yang Xun, Zhu Ming, Xue Hongxi, Bian Jinian, Hong Xianlong, "A Platform for System-on-a-chip Design Prototyping, " ASICON'2001, Shanghai, pp. 781-784, Sep. 2001.
277. Liu Jianhua, Zhu Ming, Bian Jinian, Xue Hongxi, "A debug sub-system for embedded-system co-verification, " ASICON'2001, Shanghai, pp. 777-780, Sep. 2001.
279. Krstic, J.-J. Liou, Y.-M. Jiang and K.-T. Cheng, "Delay Testing Considering Crosstalk-Induced Effects," Proceedings of International Test Conference, October, 2001.
280. Fang Shuzhou, Wang Zeyi and Hong Xianlong, "A Proof of Boundary Integral Equations of Minimum Order for the Calculation of 3-D Eddy Current Problem, " ASICON2001, Shanghai, China, October 2001.
281. Dong Sheqin, Hong Xianlong, Wu Yuliang, Xiu Zhong and Gu Jun, "VLSI Placement with Pre-placed Modules Based on Less Flexibility First Principles, " ASICON2001, Shanghai, China, October 2001.
282. Jing Tong, Hong Xianlong, Bao Haiyun, Cai Yici, Xu Jingyu, Wang Yuan and Gu Jun, "An Efficient Congestion Optimization Algorithm for Global Routing Based on Search Space Traversing Technology, " ASICON2001, Shanghai, China, October 2001.
283. Ma Yuchun, Hong Xianlong, Dong Sheqin Cai Yici, Cheng Chung-Kuan and Gu Jun, "A Compact Algorithm for Placement Design Using Corner Block List Representation, " ASICON2001, Shanghai, China, October 2001.
284. Zhou Shuo, Dong Sheqin, Wu Xiaohai and Hong Xianlong, "Integrated Floorplanning and Power Supply Planning, " ASICON2001, Shanghai, China, October 2001.
285. Lu Feng, Bian Jinian, Xue Hongxi, "EVBCS: New Equivalence Verification Algorithm Based on OBDD and Circuit Structure, " ASICON'2001, Shanghai, pp. 190-193, Sep. 2001.
286. Ma Yuchun, Hong Xianlong, Dong Sheqin, Cai Yici, Chung-Kuan Cheng and Gu Jun "Floorplanning with Abutment Constraints Based on Corner Block List, " Integration, the VLSI Journal 31 pp 65-77, Netherlands, 2001.
287.
J.-R. Huang,
C.K. Ong, K.T. Cheng, and C.-W. Wu, "An FPGA-based reconfigurable
functional tester for memory chips," in Proc. Ninth IEEE Asian Test Symp.
(ATS), Taipei, Dec. 2000, pp. 51-57.
288.
C.-W. Wang,
C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, "A built-in
self-test and self-diagnosis scheme for embedded SRAM," in Proc. Ninth
IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 45-50.
289. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "A testable/fault-tolerant FFT processor design," in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 429-433.
290. L. Li, X. Yu, C.-W. Wu, and Y. Min, "A waveform simulator based on Boolean process," in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 145-150.
291. C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, "BRAINS: A BIST complier for embedded memories," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299-307.
292. Y.-T. Hsing, C.-W. Wang, C.-W. Wu, C.-T. Huang, and C.-W. Wu, "Failure factor based yield enhancement for SRAM designs," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2000, pp. 20-28.
293.
Y.-L. Peng,
J.-J. Liou, C.-T. Huang, and C.-W. Wu, "An application-independent delay
testing methodology for island-style FPGA," in Proc. IEEE Int. Symp.
Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2000, pp.
478-486.13.
294.
C.-F. Wu,
C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, "Error catch and
analysis for semiconductor memories using March tests," in Proc. IEEE Int.
Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468-471.
295.
K.-J. Lin and
C.-W. Wu, "A low-power CAM design for LZ data compression," IEEE
Transactions on Computers, vol. 49, no. 10, pp. 1139-1145, Oct. 2000.
296. C.-Y. Su and C.-W. Wu, "A probabilistic model for path delay fault testing," J. Inform. Science and Engineering, vol. 16, no. 5, pp. 783-794, Sept. 2000.
297. C.-T. Huang and C.-W. Wu, "High-speed easily testable galois-field inverter," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 909-918, Sept. 2000.
298. J.-F. Li, S.-K. Lu, S.-A. Hwang, and C.-W. Wu, "Easily testable and fault tolerant FFT butterfly networks," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 919-929, Sept. 2000.
299. B.-H. Lin, S.-H. Shieh, and C.-W. Wu, "A fast signature computation algorithm for LFSR and MISR," IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 19, no. 9, pp. 1031-1040, Sept. 2000.
300. J.-H. Hong, P.-Y. Tsai, and C.-W. Wu, "Interleaving schemes for a systolic RSA public-key cryptosystem based on an improved Montgomery's algorithm," in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 163-166.
301. C.-H. Wu, J.-H. Hong, and C.-W. Wu, "An RSA cryptosystem based on the Chinese Remainder Theorem," in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 167-170.
302. S.-H. Shieh and C.-W. Wu, "Carry-free adder design using asymmetric high-radix signed-digit number system," in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 183-186.
303. K.-L. Cheng and C.-W. Wu, "Neighborhood pattern-sensitive fault testing for semiconductor memories," in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 401-404.
304. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "BIST and diagnosis of fully logic blocks in FPGAs," in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 413-416.
305. Li Wei, CaiYici and Hong Xianlong, "Power/Ground Networks Of Floating Pad Design And Optimization, " ICCCAS2002, Chengdu, June 2000.
306. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "Built-in self-test and fault diagnosis for lookup table FPGAs," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Geneva, May 2000, pp. I-80 - I-83.
307. K.-J. Lin and C.-W. Wu, "Testing content-addressable memories using functional fault models and March-like algorithms," IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 19, no. 5, pp. 577-588, May 2000.
308. C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, "Simulation-based test algorithm generation for random access memories," in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000, pp. 291-296.
309. J.-M. Lu and C.-W. Wu, "Cost and benefit models for logic and memory BIST," in Proc. Design, Automation and Test in Europe (DATE), Paris, Mar. 2000, pp. 710-714.
310. J.-H. Hong and C.-W. Wu, "Radix-4 modular multiplication and exponentiation algorithms for the rsa public-key cryptosystem," in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 565-570.
311. C.-T. Huang, J.-R. Huang, and C.-W. Wu, "A programmable built-in self-test core for embedded memories," in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 11-12.
312. C.-F. Wu and C.-W. Wu, "Testing and diagnosing dynamic reconfigurable FPGA," VLSI Design, vol. 10, no. 3, pp. 321-333, 2000.