Interconnect-Centric Design Project

As the integrated circuits (ICs) are scaled into nanometer dimensions and operate in giga-hertz frequencies, interconnects
have become critical in determining system performance and reliability. This project focuses in developing an interconnect-centric design flow, including interconnect
planning, interconnect synthesis, and interconnect layout, which allows interconnect design and optimization to be properly considered at every level of the design process.  Efficient interconnect performance estimation models and tools at various levels are also developed to support such an interconnect-centric design flow.

1. J. Cong, "An Interconnect-Centric Design Flow for Nanometer Technologies," Proceedings of the IEEE, vol. 89, No. 4, April 2001, pp 505-528
2. C.-C. Chang and J. Cong, "Pseudopin Assignment with Crosstalk Noise Control,", IEEE Trans. on Computer-Aided Design, May 2001, pp 598-611
3. J. Cong, J. Fang and K.-Y. Khoo, "DUNE - A Multilayer Gridless Routing System," IEEE Trans. on Computer-Aided Design, May 2001, pp 633-647
4. J. Cong and M. Romesis "Performance-driven Multi-level Clustering with Application to Hierarchical FPGA Mapping" Proc. 38th ACM/IEEE Design Automation Conf., June, 2001, pp. 389-394
5. T. Chan, J. Cong, T. Kong and J. Shinnerl "Multilevel Optimization for Large-scale Circuit Placement," Proc. IEEE International Conference on Computer Aided Design, San Jose, CA., Nov 2000, pp.171-176
6. J. Cong and S. Lim, "Physical Planning with Retiming,", Proc. IEEE International Conference on Computer Aided Design, San Jose, CA., Nov 2000, pp. 2-7
7. J. Cong, S. Lim and C. Wu, "Performance-driven Multi-level and Multiway Partition with Retiming,", Proc. ACM/IEEE 37th Design Automation Conference, Los Angeles, CA., June 2000, pp. 274-279
8. C. Chang, J. Cong, D. Pan, and X. Yuan, "Physical Hierarchy Generation with Routing Congestion and Control," Proc. International Symposium on Physical Design, pp36-41, San Diego, California, April 2002.