mGP

Mutlilevel Global Placement

VLSI CAD LAB
Department of Computer Science
University of California, Los Angeles


Recent studies suggest that synthesis and optimization under the physical hierarchy is a promising way to achieve timing closure between synthesis and layout for deep submicron designs. In UCLA VLSI CAD LAB, we focus on how to build a good physical hierarchy for performance optimization. The logical hierarchy is first flattened to the extent that we are certain circuit elements in each module have ``physical locality'' i.e., the circuits in a module should physically stay together, and then coarse/global placement is performed on this flattened design to place the placeable objects and generate a physical hierarchy.

Overview
mGP (formly called mPG), a multilevel global/coarse placement framework which is based on the multilevel optimization paradigm, is developed for physical hierarchy generation. The placement engine is based on the simulated-annealing technique because of its flexibility of integrating various design objectives and handling constraints. It can suport large-scale standard-cell placement, mixed-sized (standard-cells mixed with macros) placement for wirelength minimization and routability optimization.

Reference
  1. C.-C. Chang, J. Cong, D. Pan, and X. Yuan, "Multilevel Global Placement with Congestion Control," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp. 395-409, April 2003.
  2. C.-C. Chang, J. Cong, and X. Yuan, "Multi-level Placement for Large-Scale Mixed-Size IC Designs,", Proc. Asia South Pacific Design Automation Conference, pp 325-330, January 2003.
  3. C-C. Chang, J. Cong, Z. Pan and X. Yuan, "Physical Hierarchy Generation with Routing Congestion Control," Proc. International Symposium on Physical Design, pp36-41, San Diego, California, April 2002.

Download
  • Binary code of mGP under Solaris
  • Benchmarks used for testing

  • Related Links
  • GSRC bookshelf placement slot
  • VLSI CAD LAB in UCLA
  • Optimality Study of VLSI CAD Algorithms

  • Acknowledgment
    This project is supported in part by Semiconductor Research Corporation under contracts 98-DJ-605 and 2001-TJ-910, National Science Foundation under the grant CCR-0096383,
    a Faculty Partnership Award from IBM Corporation, and grants from Intel Corporation and Fujitsu Laboratories of America under the California MICRO program.

    Please direct your questions, comments and bug reports to mgp@ballade.cs.ucla.edu.
     



    Copyright  2001-2003.  The Regents of the University of California.
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