|
|
Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail RomesisLast updated: Apr 5, 2005 |
MEVA (Microarchitecture Evaluation with
Physical Planning) was developed at the VLSI CAD Lab, Dept. Computer Science,
UCLA. Click here
to download the release package (Linux).
MEVA takes the following inputs:
· -format: The type of input format. If it is v, the input file is in Verilog (restricted set of commands supported, click here for an example file). If it is x, the input file is in an internal group format (click here for more information).
· -f: The name of the input file
· -timingOn: If 1, timing optimization is performed, otherwise only wirelength optimization.
· -pipe: If 1, perform interconnect pipelining, otherwise cycle time (or wirelength) optimization.
· -whitespace: The amount of whitespace, in percent of the total area.
· -patoma: If 1, run partitioning-driven floorplanning (based on PATOMA), otherwise perform simulated annealing-based optimization
· -reshapable: If 1, the blocks are allowed to be reshaped, otherwise their dimensions are fixed (although they can still be rotated).
· -t: Name of top level module (only for verilog format)
· -c: Name of library file (only for verilog format, example here).
· -areaWeight : percentage of area optimization (only for simulated annealing optimization)
· -numMoves: number of moves per block per temperature (only for simulated annealing optimization)
· -flSuccess: number of successful floorplans generated
· -fix_freq: fixed frequency (only when performing interconnect pipelining, in GHz)
· -outPlotFile: The name of output file (need gnuplot to visualize)