module BPRED ( 
ftq_in,
ftq_bpred_stall,
ren_com4,
// outputs
bpred_out
);

input [39:0] ftq_in;
input ftq_bpred_stall;
input [59:0] ren_com4;

output [39:0] bpred_out;

endmodule


module S12_Latch (
clock,
bpred_out,
// outputs
ftq_in
);

input clock;
input [39:0] bpred_out;

output [39:0] ftq_in;

endmodule

module FETCHQ(
ftq_in,
ftq_ifetch_stall,
ftq_out,
ftq_bpred_stall
);

input [39:0] ftq_in;
input ftq_ifetch_stall;

output [39:0] ftq_out;
output ftq_bpred_stall;

endmodule

module S23_Latch(
  clock,
  ftq_out,
  bpred_stall,
  // outputs
  ifetch_in,
  ftq_bpred_stall
);

input clock;
input [39:0] ftq_out;
input bpred_stall;

output [39:0] ifetch_in;
output ftq_bpred_stall;

endmodule


module IFETCH (
clock,
ifetch_in,
ifetch_rob_full,
biu_ifetch_out,
//outputs
ifetch_o1, ifetch_o2, ifetch_o3, ifetch_o4,
ftq_stall,
ifetch_to_biu
);

input clock;
input [39:0] ifetch_in;
input ifetch_rob_full;
input [127:0] biu_ifetch_out;

output [32:0] ifetch_o1;
output [32:0] ifetch_o2;
output [32:0] ifetch_o3;
output [32:0] ifetch_o4;
output ftq_stall;
output [32:0] ifetch_to_biu;
endmodule

module S34_Latch(
clock,
ifetch_o1, ifetch_o2, ifetch_o3, ifetch_o4,
ftq_stall,
ifetch_to_biu,
//outputs
rob_i1,rob_i2,rob_i3,rob_i4,
ftq_ifetch_stall,
biu_ifetch_in
);

input clock;
input [32:0] ifetch_o1;
input [32:0] ifetch_o2;
input [32:0] ifetch_o3;
input [32:0] ifetch_o4;
input ftq_stall;
input [32:0] ifetch_to_biu;

output [32:0] rob_i1;
output [32:0] rob_i2;
output [32:0] rob_i3;
output [32:0] rob_i4;
output ftq_ifetch_stall;
output [32:0] biu_ifetch_in;
endmodule


module ROB(
clock,
rob_i1, rob_i2, rob_i3, rob_i4,
rob_ex11, rob_ex12, rob_ex13, rob_ex14, rob_ex15,
rob_ex21, rob_ex22, rob_ex23, rob_ex24, rob_ex25,
rob_ex31, rob_ex32, rob_ex33, rob_ex34, rob_ex35,
rob_ex41, rob_ex42, rob_ex43, rob_ex44, rob_ex45,
rob_lsu1, rob_lsu2, rob_lsu3, rob_lsu4,

rob_o1, rob_o2, rob_o3, rob_o4,
rob_com1, rob_com2, rob_com3, rob_com4,

rob_full
);

input clock;
input [32:0] rob_i1;
input [32:0] rob_i2;
input [32:0] rob_i3;
input [32:0] rob_i4;
input [87:0] rob_ex11;
input [87:0] rob_ex12;
input [87:0] rob_ex13;
input [87:0] rob_ex14;
input [87:0] rob_ex15;
input [87:0] rob_ex21;
input [87:0] rob_ex22;
input [87:0] rob_ex23;
input [87:0] rob_ex24;
input [87:0] rob_ex25;
input [87:0] rob_ex31;
input [87:0] rob_ex32;
input [87:0] rob_ex33;
input [87:0] rob_ex34;
input [87:0] rob_ex35;
input [87:0] rob_ex41;
input [87:0] rob_ex42;
input [87:0] rob_ex43;
input [87:0] rob_ex44;
input [87:0] rob_ex45;

input [11:0] rob_lsu1;
input [11:0] rob_lsu2;
input [11:0] rob_lsu3;
input [11:0] rob_lsu4;

output [53:0] rob_o1;
output [53:0] rob_o2;
output [53:0] rob_o3;
output [53:0] rob_o4;

output [59:0] rob_com1;
output [59:0] rob_com2;
output [59:0] rob_com3;
output [59:0] rob_com4;

output rob_full;
endmodule

module S45_latch(
clock,
rob_o1, rob_o2, rob_o3, rob_o4,
rob_com1,rob_com2,rob_com3,rob_com4,
rob_full,
// outputs
ifetch_rob_full,
ren_i1,ren_i2,ren_i3,ren_i4,
ren_com1, ren_com2, ren_com3, ren_com4
);

input clock;
input  [53:0] rob_o1;
input  [53:0] rob_o2;
input  [53:0] rob_o3;
input  [53:0] rob_o4;

input  [59:0] rob_com1;
input  [59:0] rob_com2;
input  [59:0] rob_com3;
input  [59:0] rob_com4;
input rob_full;

output ifetch_rob_full;
output  [53:0] ren_i1;
output  [53:0] ren_i2;
output  [53:0] ren_i3;
output  [53:0] ren_i4;

output  [59:0] ren_com1;
output  [59:0] ren_com2;
output  [59:0] ren_com3;
output  [59:0] ren_com4;

endmodule

module RENAME(
clock,
ren_i1, ren_i2, ren_i3, ren_i4,
ren_com1, ren_com2, ren_com3, ren_com4,
rob_lsu1, rob_lsu2, rob_lsu3, rob_lsu4,
// outputs
ren_o1, ren_o2, ren_o3, ren_o4
);

input clock;
input  [53:0] ren_i1;
input  [53:0] ren_i2;
input  [53:0] ren_i3;
input  [53:0] ren_i4;
input  [59:0] ren_com1;
input  [59:0] ren_com2;
input  [59:0] ren_com3;
input  [59:0] ren_com4;
input [11:0] rob_lsu1;
input [11:0] rob_lsu2;
input [11:0] rob_lsu3;
input [11:0] rob_lsu4;

output [71:0] ren_o1;
output [71:0] ren_o2;
output [71:0] ren_o3;
output [71:0] ren_o4;

endmodule

module S56_latch(
clock,
ren_o1, ren_o2, ren_o3, ren_o4,
sch1_ren_in, sch2_ren_in, sch3_ren_in, sch4_ren_in
);

input clock;
input [71:0] ren_o1;
input [71:0] ren_o2;
input [71:0] ren_o3;
input [71:0] ren_o4;

output [287:0] sch1_ren_in;
output [287:0] sch2_ren_in;
output [287:0] sch3_ren_in;
output [287:0] sch4_ren_in;

endmodule


module SCHEDULER (
clock,
sch_ren_in,
rob_lsu,
mdh_out,

sch_out
);

input clock;
input [287:0] sch_ren_in;
input [19:0] mdh_out;
input [11:0] rob_lsu;
output [143:0] sch_out;
endmodule

module S67_latch(
clock,
sch_out,
reg_in
);

input clock;
input [143:0] sch_out;
output [143:0] reg_in;
endmodule

module REGFILE(
clock,
reg_in,
rob_lsu,
reg2reg_in,

reg_out,
reg2reg_out
);

input clock;
input [143:0] reg_in;
input [11:0] rob_lsu;
input [299:0] reg2reg_in;

output [231:0] reg_out;
output [299:0] reg2reg_out;
endmodule

module S78_latch(
clock,
reg_out,
ex_in
);

input clock;
input [231:0] reg_out;
output [231:0] ex_in;
endmodule

module INTALU(
clock,
ex_in,
ex_out
);
input clock;
input [231:0] ex_in;
output [87:0] ex_out; 
endmodule

module FPALU(
clock,
ex_in,
ex_out
);
input clock;
input [231:0] ex_in;
output [87:0] ex_out; 
endmodule

module INTMUL (
clock,
ex_in,
ex_out
);
input clock;
input [231:0] ex_in;
output [87:0] ex_out; 
endmodule

module FPMUL (
clock,
ex_in,
ex_out
);
input clock;
input [231:0] ex_in;
output [87:0] ex_out; 
endmodule

module S89_latch (
clock,
ex1_out, ex2_out, ex3_out, ex4_out, ex5_out,

rob_ex1, rob_ex2, rob_ex3, rob_ex4, rob_ex5
);

input clock;
input [87:0] ex1_out;
input [87:0] ex2_out;
input [87:0] ex3_out;
input [87:0] ex4_out;
input [87:0] ex5_out;

output [87:0] rob_ex1;
output [87:0] rob_ex2;
output [87:0] rob_ex3;
output [87:0] rob_ex4;
output [87:0] rob_ex5;

endmodule

module LSU (
clock,
rob_ex1, rob_ex2,
biu_lsu_data_bus,

rob_lsu, biu_lsu_addr_bus
);

input clock;
input [87:0] rob_ex1;
input [87:0] rob_ex2;
input [127:0] biu_lsu_data_bus;

output [11:0] rob_lsu;
input [32:0] biu_lsu_addr_bus; 
endmodule


module MDH (
clock,
rob_ex11, rob_ex12, 
rob_ex21, rob_ex22,
rob_ex31, rob_ex32,
rob_ex41, rob_ex42,

mdh_out1, mdh_out2, mdh_out3, mdh_out4
);

input clock;
input [87:0] rob_ex11;
input [87:0] rob_ex12;
input [87:0] rob_ex21;
input [87:0] rob_ex22;
input [87:0] rob_ex31;
input [87:0] rob_ex32;
input [87:0] rob_ex41;
input [87:0] rob_ex42;

output [19:0] mdh_out1;
output [19:0] mdh_out2;
output [19:0] mdh_out3;
output [19:0] mdh_out4;

endmodule

module L2CACHE(
  clock,
  from_biu,
  to_biu
);

input clock;
input [127:0] from_biu;
output [32:0] to_biu;

endmodule

module BIU (
clock,
biu_ifetch_addr_bus,
biu_lsu_addr_bus,
biu_l2_data_bus,
//biu_memory_data_bus,
//output
biu_ifetch_data_bus,
biu_lsu_data_bus,
biu_l2_addr_bus
//biu_memory_addr_bus
);

input clock;
input [32:0] biu_ifetch_addr_bus;
output [32:0] biu_lsu_addr_bus;
output [127:0] biu_l2_data_bus;
//input [255:0] biu_memory_data_bus;

//output [32:0] biu_memory_addr_bus;
input [32:0] biu_l2_addr_bus;
output [127:0] biu_lsu_data_bus;
output [127:0] biu_ifetch_data_bus;
endmodule
//// Top level processor description /////////////

module PROC(
clock,
//biu_memory_data_bus,
//biu_memory_addr_bus
);

input clock;
//input [255:0] biu_memory_data_bus;
//output [32:0] biu_memory_addr_bus;

// Local wires for this module

wire [39:0] ftq_in;
wire [39:0] bpred_out;
wire ftq_bpred_stall;

wire bpred_stall;

wire ftq_ifetch_stall;
wire[39:0] ftq_out;
wire [39:0]ifetch_in;

wire [32:0] ifetch_o1;
wire [32:0] ifetch_o2;
wire [32:0] ifetch_o3;
wire [32:0] ifetch_o4;
wire ftq_stall;
wire ifetch_rob_full;
wire [32:0] ifetch_to_biu;

wire [32:0] rob_i1;
wire [32:0] rob_i2;
wire [32:0] rob_i3;
wire [32:0] rob_i4;

wire [53:0] rob_o1;
wire [53:0] rob_o2;
wire [53:0] rob_o3;
wire [53:0] rob_o4;

wire [59:0] rob_com1;
wire [59:0] rob_com2;
wire [59:0] rob_com3;
wire [59:0] rob_com4;

wire [87:0] rob_ex11;
wire [87:0] rob_ex12;
wire [87:0] rob_ex13;
wire [87:0] rob_ex14;
wire [87:0] rob_ex15;
wire [87:0] rob_ex21;
wire [87:0] rob_ex22;
wire [87:0] rob_ex23;
wire [87:0] rob_ex24;
wire [87:0] rob_ex25;
wire [87:0] rob_ex31;
wire [87:0] rob_ex32;
wire [87:0] rob_ex33;
wire [87:0] rob_ex34;
wire [87:0] rob_ex35;
wire [87:0] rob_ex41;
wire [87:0] rob_ex42;
wire [87:0] rob_ex43;
wire [87:0] rob_ex44;
wire [87:0] rob_ex45;

wire [11:0] rob_lsu1;
wire [11:0] rob_lsu2;
wire [11:0] rob_lsu3;
wire [11:0] rob_lsu4;

wire rob_full;

wire [53:0] ren_i1;
wire [53:0] ren_i2;
wire [53:0] ren_i3;
wire [53:0] ren_i4;

wire [71:0] ren_o1;
wire [71:0] ren_o2;
wire [71:0] ren_o3;
wire [71:0] ren_o4;

wire [59:0] ren_com1;
wire [59:0] ren_com2;
wire [59:0] ren_com3;
wire [59:0] ren_com4;

wire [287:0] sch1_ren_in; // 4 instructions/cycle?
wire [287:0] sch2_ren_in; // 4 instructions/cycle?
wire [287:0] sch3_ren_in; // 4 instructions/cycle?
wire [287:0] sch4_ren_in; // 4 instructions/cycle?

wire [143:0] sch1_out; // 2 instructions/cycle
wire [143:0] sch2_out; // 2 instructions/cycle
wire [143:0] sch3_out; // 2 instructions/cycle
wire [143:0] sch4_out; // 2 instructions/cycle

wire [143:0] reg1_in;
wire [143:0] reg2_in;
wire [143:0] reg3_in;
wire [143:0] reg4_in;

wire [231:0] reg1_out; // data for 2 instructions
wire [231:0] reg2_out; // data for 2 instructions
wire [231:0] reg3_out; // data for 2 instructions
wire [231:0] reg4_out; // data for 2 instructions

wire [231:0] ex1_in;
wire [231:0] ex2_in;
wire [231:0] ex3_in;
wire [231:0] ex4_in;

wire [87:0] ex11_out;
wire [87:0] ex12_out;
wire [87:0] ex13_out;
wire [87:0] ex14_out;
wire [87:0] ex15_out;
wire [87:0] ex21_out;
wire [87:0] ex22_out;
wire [87:0] ex23_out;
wire [87:0] ex24_out;
wire [87:0] ex25_out;
wire [87:0] ex31_out;
wire [87:0] ex32_out;
wire [87:0] ex33_out;
wire [87:0] ex34_out;
wire [87:0] ex35_out;
wire [87:0] ex41_out;
wire [87:0] ex42_out;
wire [87:0] ex43_out;
wire [87:0] ex44_out;
wire [87:0] ex45_out;

wire [19:0] mdh_out1;
wire [19:0] mdh_out2;
wire [19:0] mdh_out3;
wire [19:0] mdh_out4;

wire [32:0] biu_l2_addr_bus;
wire [127:0] biu_l2_data_bus;
wire [32:0] biu_lsu_addr_bus;
wire [127:0] biu_lsu_data_bus;
wire [32:0] biu_ifetch_addr_bus;
wire [127:0] biu_ifetch_data_bus;

// ring communication among register files

wire [299:0] r1_to_r2_bus;
wire [299:0] r2_to_r3_bus;
wire [299:0] r3_to_r4_bus;
wire [299:0] r4_to_r1_bus;

/////////// stage 1 //////////////////////////

BPRED bpred(
ftq_in,
ftq_bpred_stall,
ren_com4,
// outputs
bpred_out
);

S12_Latch latch0(
clock,
bpred_out,
// outputs
ftq_in
);


//////////// stage 2 //////////////////////////


FETCHQ ftq(
ftq_in,
ftq_ifetch_stall,
ftq_out,
bpred_stall
);


S23_Latch latch1(
clock,
ftq_out,
bpred_stall,
// outputs
ifetch_in,
ftq_bpred_stall
);


//////////// stage 3 //////////////////////////


IFETCH ifetch(
clock,
ifetch_in,
ifetch_rob_full,
biu_ifetch_data_bus,
//outputs
ifetch_o1, ifetch_o2, ifetch_o3, ifetch_o4,
ftq_stall,
ifetch_to_biu
);


S34_Latch latch2(
clock,
ifetch_o1, ifetch_o2, ifetch_o3, ifetch_o4,
ftq_stall,
ifetch_to_biu,
//outputs
rob_i1,rob_i2,rob_i3,rob_i4,
ftq_ifetch_stall,
biu_ifetch_addr_bus
);

////////////// stage 4 /////////////////////////


ROB rob(
clock,
rob_i1, rob_i2, rob_i3, rob_i4,
rob_ex11, rob_ex12, rob_ex13, rob_ex14, rob_ex15,
rob_ex21, rob_ex22, rob_ex23, rob_ex24, rob_ex25,
rob_ex31, rob_ex32, rob_ex33, rob_ex34, rob_ex35,
rob_ex41, rob_ex42, rob_ex43, rob_ex44, rob_ex45,
rob_lsu1, rob_lsu2, rob_lsu3, rob_lsu4,

rob_o1, rob_o2, rob_o3, rob_o4,
rob_com1, rob_com2, rob_com3, rob_com4,

rob_full
);

S45_latch latch3(
clock,
rob_o1, rob_o2, rob_o3, rob_o4,
rob_com1,rob_com2,rob_com3,rob_com4,
rob_full,
// outputs
ifetch_rob_full,
ren_i1,ren_i2,ren_i3,ren_i4,
ren_com1, ren_com2, ren_com3, ren_com4
);

////////// stage 5 /////////////////////////////////


RENAME rename(
clock,
ren_i1, ren_i2, ren_i3, ren_i4,
ren_com1, ren_com2, ren_com3, ren_com4,
rob_lsu1, rob_lsu2, rob_lsu3, rob_lsu4,
// outputs
ren_o1, ren_o2, ren_o3, ren_o4
);

S56_latch latch4(
clock,
ren_o1, ren_o2, ren_o3, ren_o4,
sch1_ren_in, sch2_ren_in, sch3_ren_in, sch4_ren_in
);

//////////// single cluster definition here//////////////////


//// stage 6 /////////////
SCHEDULER sch1(
clock,
sch1_ren_in,
rob_lsu1,
mdh_out1,

sch1_out
);

S67_latch latch5(
clock,
sch1_out,
reg1_in
);

//// stage 7 /////////////

REGFILE reg1(
clock,
reg1_in,
rob_lsu1,
r4_to_r1_bus,

reg1_out,
r1_to_r2_bus
);

S78_latch latch6(
clock,
reg1_out,
ex1_in
);

//// stage 8 /////////////

INTALU ex11(
clock,
ex1_in,
ex11_out
);

INTALU ex12(
clock,
ex1_in,
ex12_out
);

FPALU ex13(
clock,
ex1_in,
ex13_out
);

INTMUL ex14(
clock,
ex1_in,
ex14_out
);

FPMUL ex15(
clock,
ex1_in,
ex15_out
);

S89_latch latch7(
clock,
ex11_out, ex12_out, ex13_out, ex14_out, ex15_out,

rob_ex11, rob_ex12, rob_ex13, rob_ex14, rob_ex15
);

LSU lsu1(
clock,
rob_ex11, rob_ex12,
biu_lsu_data_bus,

rob_lsu1, biu_lsu_addr_bus
);

//////// cluster 2 //////////////////////
//// stage 6 /////////////
SCHEDULER sch2(
clock,
sch2_ren_in,
rob_lsu2,
mdh_out2,

sch2_out
);

S67_latch latch8(
clock,
sch2_out,
reg2_in
);

//// stage 7 /////////////

REGFILE reg2(
clock,
reg2_in,
rob_lsu2,
r1_to_r2_bus,

reg2_out,
r2_to_r3_bus
);

S78_latch latch9(
clock,
reg2_out,
ex2_in
);

//// stage 8 /////////////

INTALU ex21(
clock,
ex2_in,
ex21_out
);

INTALU ex22(
clock,
ex2_in,
ex22_out
);

FPALU ex23(
clock,
ex2_in,
ex23_out
);

INTMUL ex24(
clock,
ex2_in,
ex24_out
);

FPMUL ex25(
clock,
ex2_in,
ex25_out
);

S89_latch latch10(
clock,
ex21_out, ex22_out, ex23_out, ex24_out, ex25_out,

rob_ex21, rob_ex22, rob_ex23, rob_ex24, rob_ex25
);

LSU lsu2(
clock,
rob_ex21, rob_ex22,
biu_lsu_data_bus,

rob_lsu2, biu_lsu_addr_bus
);

/////////// cluster 3 ////////////////////
//// stage 6 /////////////
SCHEDULER sch3(
clock,
sch3_ren_in,
rob_lsu3,
mdh_out3,

sch3_out
);

S67_latch latch11(
clock,
sch3_out,
reg3_in
);

//// stage 7 /////////////

REGFILE reg3(
clock,
reg3_in,
rob_lsu3,
r2_to_r3_bus,

reg3_out,
r3_to_r4_bus
);

S78_latch latch12(
clock,
reg3_out,
ex3_in
);

//// stage 8 /////////////

INTALU ex31(
clock,
ex3_in,
ex31_out
);

INTALU ex32(
clock,
ex3_in,
ex32_out
);

FPALU ex33(
clock,
ex3_in,
ex33_out
);

INTMUL ex34(
clock,
ex3_in,
ex34_out
);

FPMUL ex35(
clock,
ex3_in,
ex35_out
);

S89_latch latch13(
clock,
ex31_out, ex32_out, ex33_out, ex34_out, ex35_out,

rob_ex31, rob_ex32, rob_ex33, rob_ex34, rob_ex35
);

LSU lsu3(
clock,
rob_ex31, rob_ex32,
biu_lsu_data_bus,

rob_lsu3, biu_lsu_addr_bus
);

/////// cluster 4 //////////////////////////////
//// stage 6 /////////////
SCHEDULER sch4(
clock,
sch4_ren_in,
rob_lsu4,
mdh_out4,

sch4_out
);

S67_latch latch14(
clock,
sch4_out,
reg4_in
);

//// stage 7 /////////////

REGFILE reg4(
clock,
reg4_in,
rob_lsu4,
r3_to_r4_bus,

reg4_out,
r4_to_r1_bus
);

S78_latch latch15(
clock,
reg4_out,
ex4_in
);

//// stage 8 /////////////

INTALU ex41(
clock,
ex4_in,
ex41_out
);

INTALU ex42(
clock,
ex4_in,
ex42_out
);

FPALU ex43(
clock,
ex4_in,
ex43_out
);

INTMUL ex44(
clock,
ex4_in,
ex44_out
);

FPMUL ex45(
clock,
ex4_in,
ex45_out
);

S89_latch latch16(
clock,
ex41_out, ex42_out, ex43_out, ex44_out, ex45_out,
rob_ex41, rob_ex42, rob_ex43, rob_ex44, rob_ex45
);

LSU lsu4(
clock,
rob_ex41, rob_ex42,
biu_lsu_data_bus,

rob_lsu4, biu_lsu_addr_bus
);

///// global structures //////////////////

MDH mdh(
clock,
rob_ex11, rob_ex12, 
rob_ex21, rob_ex22,
rob_ex31, rob_ex32,
rob_ex41, rob_ex42,

mdh_out1, mdh_out2, mdh_out3, mdh_out4
);

///////// Bus interface unit //////////////////

BIU biu(
clock,
biu_ifetch_addr_bus,
biu_lsu_addr_bus,
biu_l2_data_bus,
//biu_memory_data_bus,
//output
biu_ifetch_data_bus,
biu_lsu_data_bus,
biu_l2_addr_bus
//biu_memory_addr_bus
);

///////// L2 cache unit ///////////////////////

L2CACHE l2cache(
  clock,
  biu_l2_data_bus,
  biu_l2_addr_bus
);



endmodule