xPilot: Platform-based Behavior Synthesis System

The xPilot Team:

xPilot Overview

xPilot is a behavior synthesis system from C or SystemC to RTL code with necessary design constraints. The advantages of xPilot includes: platform-based behavior and system synthesis, communication/interconnect-centric approach, advanced algorithms for platform-based, communication-centric optimization, and promising results demonstrated on available FPGAs. The two main synthesis modules of xPilot are:
Processor-based synthesis

Application-Specific Instruction-set Processors (ASIPs) and Application-Specific Network Processor (ASPN) have gained popularity in production chips as well as in the research community. They offer a viable solution to tradeoff between efficiency and flexibility. For example, modern field programmable devices can hold tens of soft processors in a single FPGA, which allows the designers to build a multiprocessor system by exploiting the parallelism in applications. xPilot focuses on the synthesis/mapping process with the goal of optimizing performance, resource usage, interconnection, and throughput. The above graph shows the synthesis flow targeting at ASPN.
Hardware-based synthesis

Behavioral synthesis is an automated design process that compiles functional and/or algorithmic descriptions into optimized hardware architectures. It has long been identified as one of the critical technologies for enabling the transition to the higher level of abstraction. Unfortunately, it stumbled in its debut on the EDA marketplace during the mid-1990s and so far has had a limited adoption among chip designers. With the billion-transistor chip on the horizon, the design complexity of integrated circuit systems is outgrowing the capabilities of current RTL methods. This brought about a renewed interest in behavioral synthesis, and innovations are required to address the new challenges in nanometer IC designs. xPilot aims to provide novel platform-based synthesis technologies to optimize logic, interconnects, performance, and power simultaneously at the high level. The ultimate goal is to improve both design productivity and quality of results. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.
Objectives:
Potential impact:
Technology transfer:
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