The xPilot System

xPilot is a behavior synthesis system from C or SystemC to RTL code with necessary design constraints. The advantages of xPilot includes: platform-based behavior and system synthesis, communication/interconnect-centric approach, advanced algorithms for casinos platform-based, communication-centric optimization, and promising results demonstrated on available FPGAs. The two main synthesis modules of xPilot are:

Processor-based synthesis: target at configurable processors, multi-cores, and multi-processors.
Hardware-based synthesis: target at highly customized devices, such as FPGA and ASIC.

Processor-based synthesis

Application-Specific Instruction-set Processors (ASIPs) and Application-Specific Network Processor (ASPN) have gained popularity in production chips as well as in the research community. They offer a viable solution to tradeoff between efficiency and flexibility. For example, modern field programmable devices can hold tens of soft processors in a single FPGA, which allows the designers to build a multiprocessor system by exploiting the parallelism in applications. xPilot focuses on the synthesis/mapping process with the goal of optimizing performance, resource usage, interconnection, and throughput. The above graph shows the synthesis flow targeting at ASPN.

Hardware-based synthesis

Behavioral synthesis is an automated design process that compiles functional and/or algorithmic descriptions into optimized hardware architectures. It has long been identified as one of the critical technologies for enabling the transition to the higher level of abstraction. Unfortunately, it stumbled in its debut on the EDA marketplace during the mid-1990s and so far has had a limited adoption among chip designers. With the billion-transistor chip on the horizon, the design complexity of integrated circuit systems is outgrowing the capabilities of current RTL methods. This brought about a renewed interest in behavioral synthesis, and innovations are required to address the new challenges in nanometer IC designs. xPilot aims to provide novel platform-based synthesis technologies to optimize logic, interconnects, performance, and power simultaneously at the high level. The ultimate goal is to improve both design productivity and quality of results. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.

Objectives:

Automatically synthesize the high-level behavioral descriptions (C/SystemC) to silicon platforms (e.g., FPGAs, Structure ASICs, ASICs, etc.)
Explore application-specific design space basing on configurable processor platforms.
Optimize logic, interconnects, performance, and power simultaneously, which becomes extremely difficult to human designers on complex designs.

Potential impact:

Raise the design abstraction above RTL
Improve both design productivity and quality of results

Technology transfer:

The xPilot system is being licensed by AutoESL Design Technologies, Inc. as the basis for further development as an advanced commercial-strength ESL synthesis tool.

xPilot Download

Download:

xPilot-linux.

xPilot Resources

Publications:

J. Cong and W. Jiang, "Pattern-based Behavior Synthesis for FPGA Resource Reduction", Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, February 2008.
J. Cong and J. Xu, "Simultaneous FU and Register Binding Based on Network Flow Method", Design, Automation and Test in Europe (DATE 2008), Munich, Germany, March 2008.
J. Cong, G. Han, and W. Jiang, "Synthesis of an Application-Specific Soft Multiprocessor System ," Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2007.
J. Cong, Y. Fan, and W. Jiang, "Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture," Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2006.
J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "Platform-Based Behavior-Level and System-Level Synthesis," Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006. (Invited Paper)
J. Cong and Z. Zhang, "An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 433-438, July 2006.
J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang, "Behavior and Communication Co-Optimization for Systems with Sequential Communication Media," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.
D. Chen, J. Cong, Y. Fan and J. Xu, "Optimality Study of Resource Binding with Multi-Vdds," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 580-585, July 2006.
D. Chen, J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "xPilot: A Platform-Based Behavioral Synthesis System" SRC TechCon'05, Portland, OR, Nov, 2005.
J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng, "Bitwidth-Aware Scheduling and Binding in High-Level Synthesis," Proceedings of the Asia South Pacific Design Automation Conference, pp. 856-861, January 2005.
J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman and Z. Zhang, "Instruction Set Extension with Shadow Registers for Configurable Processors," Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 99-106, February 2005.
J. Cong, G. Han and Z. Zhang, "Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors," Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 263-270, November 2005.
J. Cong, Y. Fan, G. Han, and Z. Zhang, "Application-Specific Instruction Generation for Configurable Processor Architectures," Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 183 - 189, February 2004.
J. Cong, Y. Fan, and Z. Zhang, "Architecture-Level Synthesis for Automatic Interconnect Pipelining," Proceedings of the Design Automation Conference, pp. 602 - 607, June 2004.
J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang, "Architecture and Synthesis for On-Chip Multi-Cycle Communication," IEEE Transactions on Computer-Aided Design of Integrate d Circuits and Systems, pp.550 - 564, April 2004
D. Chen, and J. Cong, "Register Binding and Port Assignment for Multiplexer Optimization," Proceedings of the Asia Pacific Design Automation Conference, pp. 68 - 73, January 2004.
J. Cong, Y. Fan, X. Yang and Z. Zhang, "Architecture and Synthesis for Multi-Cycle Communication," ACM/SIGDA Proceedings of 2003 International Symposium on Physical Design, Monterey, California, pp. 190-196, April 2003.(Invited paper)

Presentations:

"Platform-Based Based Behavior Behavior-Level and System Level and System-Level Synthesis Level Synthesis", The 2006 Electronic Design Processes Workshop, Monterey, CA, USA, Aprril 13-14, 2006 [PDF].
"xPilot: A Platform-Based System-Level Synthesis for Reconfigurable SOCs", International Symposium on Advanced Reconfigurable Systems, Kyoto, Japan, Canada, December 15-16, 2005 [PDF].
"Platform-Based Synthesis for Field Programmable SOCs", IEEE 2005 Conference on Field Programmable Technology (FPT'05), Singapore, December 11-14, 2005 [PDF].