RASP source release B 1.1 + PLAmap B 1.0

This limited source release includes the following mapping algorithms:

DAG_Map (depth minimization)  version 1.0
FlowMap  (depth optimal) version 2.1
FlowMap-r (area-delay tradeoff)  version 2.0
FlowSYN (FPGA resynthesis)  version 2.0
CutMap (simultaneous area delay minimization)  version 1.3 (This version returns optimal mapping depth by default.)
EMB_Pack (mapping for FPGAs with embedded memory blocks for area minimization while maintaining the delay)  version 1.0
EMB_PreMap (the pre-mapping processing version for EMB_Pack)  version 1.0
HeteroMap (delay optimal mapping for heterogeneous FPGAs)  version 1.0
BinaryHM and CN-HM (delay-oriented mapping for heterogeneous FPGAs with bounded resources)  version 1.0
PLAmap (delay-oriented mapping for CPLDs)+benchmarks  version B 1.0

Download the RASP Technology Mapping Limited Source Package

Download the RASP Technology Limited Source Package (Solaris only. Use a browser from Unix.)
 
 
 

RASP executable release B 2.1

This executable release includes the following mapping algorithms:

DAG_Map (depth minimization)  version 1.0
FlowMap  (depth optimal) version 2.1
TurboMap (optimal mapping with retiming)  version 1.0
FlowMap-r (area-delay tradeoff)  version 2.0
FlowSYN (FPGA resynthesis)  version 2.0
CutMap (simultaneous area delay minimization)  version 1.3 (returns optimal mapping depth by default)
ZMap (simultaneous area delay minimization)  version 1.0
EMB_Pack (mapping for FPGAs with embedded memory blocks for area minimization while maintaining the delay)  version 1.0
EMB_PreMap (the pre-mapping processing version for EMB_Pack)  version 1.0
HeteroMap (delay optimal mapping for heterogeneous FPGAs)  version 1.0
BinaryHM and CN-HM (delay-oriented mapping for heterogeneous FPGAs with bounded resources)  version 1.0
Praetor (fast area-oriented mapping for FPGAs)  version 1.0
PLAmap (delay-oriented mapping for CPLDs)  version 1.0
DAOmap (Depth-optimal Area Optimization mapping for FPGAs)  version 1.0

Download the RASP Technology Mapping Executable Package

Download the RASP Technology Mapping Executable Package (Solaris and Linux versions available. Use a browser from Unix or Linux.)
 
 
 

ACKNOWLEDGEMENT

The UCLA synthesis packages are integrated into the SIS system and uses many of the routines provided by SIS. The SIS system was  developed in UC Berkeley Electronic Research Lab.

PACKAGE CONTENT

extended sis   -- binary of extended SIS compiled with all recent UCLA FPGA/CPLD synthesis and mapping algorithms.
plamap   -- binary of plamap, a mapping algorithm for CPLD architecture.
release.statement -- to be read first.
README -- a file with similar messages as shown in this website
rasp_syn  -- a csh script of FPGA mapping
select   -- mapping result selector

 
RASP package provides a complete solution to FPGA/CPLD mapping engine. The entire flow of RASP is:
1. Gate decomposition to get K-bounded circuit, where K is the fanin limit of LUTs of the target architecture
2. Generic LUT/PLA mapping
3. Post-processing mainly for area reduction
4. Architecture specific mapping
RASP comes with a user-friendly csh script for the ease of use. However, you can modify the script or write your own based on your specific needs.

TECHNICAL REFERENCES

J. Cong, and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.

J. Cong, and Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol 2., No. 2, June 1994, pp. 137-148.

J. Cong, Y. Ding, T. Gao, and K. Chen, "LUT-Based FPGA Technology Mapping under Arbitrary Net-Delay Models," Computers & Graphics , Vol.18, No.4, 1994, 507-516.

J. Cong, and Y. Ding, "Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs," Proc. 1993 IEEE/ACM Int'l Conf. on CAD, Santa Clara, CA, Nov. 1993, pp. 110-114.

K.Chen, J.Cong, Y.Ding, A.Kahng, and P.Trajmar, "DAG-MAP: Graph-Based FPGA Technology Mapping for Delay Optimization," IEEE Design & Test of Computers, Sept. 1992

J. Cong, J. Peck, and Y. Ding, "RASP: A General Logic Synthesis System for SRAM-based FPGAs," Proc. ACM 4th Int'l Symp. on FPGA, pp. 137-143, 1996

J. Cong, and Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping," Proc. ACM 3rd Int'l Symp. on FPGA, Feb. 1995, pp. 68-74.

J. Cong, and Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rd Design Automation Conf., pp. 726-729, 1996.

J. Cong, and C. Wu, "An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design", Proc. IEEE Int'l Conf. on Computer Design, Austin, Texas, Oct. 1996, pp. 572-578.

J. Cong, and Y. Hwang, "Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping"Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, CA., Feb. 1997, pp. 35-42.

J. Cong, and C. Wu, "FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits" Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, CA., June 1997, pp. 644-649

J. Cong, and S. Xu, "Technology Mapping for FPGAs with Embedded Memory Blocks" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 179-188

J. Cong, and Y. Hwang, "Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 27-34

J. Cong, and C. Wu, "Optimal FPGA Mapping and Retiming with Efficient Initial State Computation"Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 330-335

J. Cong, and S. Xu, "Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs" Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 704-707

J. Cong, and S. Xu, "Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources"Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1998, pp. 40-45.

J. Cong, and C. Wu, "An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming" IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems vol 17, no 9, 1998, pp. 738-748

J. Cong, and Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology in LUT-based FPGA Designs" TODAES , vol 5, no 3, July 2000.

J. Cong, C. Wu, and E. Ding, "Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution" Proc. ACM Intl. Symp. on FPGA Monterey, California, pp. 29-35, February 1999.

D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architecture" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,, vol. 22, no. 10, pp. 1424-1431, October 2003

D. Chen, and J. Cong, "DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs," Proc. IEEE International Conference on Computer Aided Design, San Jose, California, November 2004.

• Xilinx, Virtex-II Pro Complete Data Sheet, Nov. 2003.

• Altera, Stratix Device Family Data Sheet, Nov. 2003.

• Altera, MAX 7000 Programmable Logic Device Family Data Sheet, June 2003.

Script of UCLA FPGA Mapping
Commands provided by UCLA FPGA/CPLD Mapping Package

Script of UCLA FPGA Mapping

Usage:    rasp_syn    circuit    -sis path    -k k    -device xc3k/xc4k    -algo algo    -relax r    -objective area/delay/tradeoff/all

Rasp_syn is a csh script for an easy usage of UCLA FPGA Mapping algorithms. In default, the input is in EQN format with extension .eqn. The output is an LUT network with/without matching information in EQN format as well. Please keep the program "select" in the current directory.
To use other data formats as BLIF or SLIF which are supported by SIS of UCB, please set FMT in rasp_syn script to blif or slif and use .blif or .slif as the name extension of the input file. The output format will be changed automatically, except the CLB matching file format, which will be kept in EQN format. For Xilinx XC3K/XC4K CLBs, the CLB clustering information will be presented as:

#CLB_number: (lut1, lut2)
lut1 = ..
lut2 = ..
There are two ways to run rasp_syn:
1. Running with single given mapping algorithm
The algorithm must be specified with option -algo algorithm. The target is K-LUT. The output circuit is in circuit.k in EQN format.
2. Running with multiple algorithms
Rasp_syn can run all the built-in algorithms automatically and return the best result (in terms of area or delay) or a set of results based on area-delay tradeoff or all the results for you.

To run multiple algorithms, you simply do not specify any algorithm with -algo option.

 
Options
 
-sis                Specify the path of sis. The default is sis and the path must be specified in the environment.

-k                 Used only in single algorithm mode. K is the input number of LUTs. The output is in circuit.k.

-device        Used only in multi-algorithm mode. This is the default mode.

            The current supported devices are:
xc3k Xilinx XC3000 Family
xc4k Xilinx XC4000 Family
-algo            Specify the mapping algorithm in single algorithm mode.
            The current supported algorithms are:
flowmap:    FlowMap
turbomap:    TurboMap
flowmap-r:    FlowMap-r
flowsyn:    FlowSYN
cutmap:    CutMap
zmap:    ZMap for delay
zma:    ZMap for area
-relax          Used only in single algorithm mode with FlowMap-r. R is the depth relaxation.

-objective   Used only in multi-algorithm mode. The objective can be:

area:    Area first. This is the default objective.
delay:    Depth first
tradeoff:    Area-delay tradeoff
all:    All the results

Commands provided by UCLA FPGA Mapping Package

1. Area-optimal mapping Commands
2. Gate Decomposition Commands
3. LUT & PLA Mapping Commands
4. Multi-output CLB Matching Commands
5.Net-Delay Data Access Commands
6. Post-Processing Commands
7. Printing Commands
8. Programmable Logic Block Generation Commands
9. Utility Commands

1. Area-optimal mapping

* vismap [ -k ] [ -t ]
 
Compute area-optimal mapping using N. Woo's VISMap algorithm.
This routine is implemmented for comparative study only.
Due to its exhaustive search nature, it is very slow.
 
-k specify the LUT fanin limit (default 5).
 
-t threshold instead of finding the optimal mapping instruct the algorithm to stop when a
solution of no more than threshold LUTs are found. By default optimal
mapping will be computed. Note: specifying a very small threshold will actually
yield the optimal mapping.

2. Gate Decomposition Commands

 
* dmig [ -k <K_value> ] [ -f ]
 
Decompose a simple gate network into a K-bounded network (i.e. each gate has no more than K inputs), or complex gates into K-bounded gates with -f option.
For obtaining a simple gate network, use sis command
"tech_decomp -a 1000 -o 1000."
-k  specifies max. gate input size K, with a default value 2.

-f  decompose complex gates in the network
 

* dogma [ -k <K_value> ]
 
Decompose a simple gate network into a 2-bounded network such that flowmap, cutmap, or zmap can obtain a best (small) depth.

-k  specifies the LUT input size K, with a default value 5.


 

3. LUT & PLA Mapping Commands

 
* dagmap [ -k <K_value> ]
 
Map a K-bounded network into a K-LUT network of small depth (might not be optimal).
Area can be further reduced by post-processing packing routines.

-k  specifies the LUT input size K, with a default value 5.
 

* flowmap [ -k <K_value> ] [-r <R_value> ] [ -s <S_value> ]
 
Map a K-bounded network into a K-LUT network of optimal depth, or within the optimal depth plus R.
Area can be further reduced by post-processing packing routines.

-k  specifies the LUT input size K, with a default value 5.

-r  specifies the relaxed depth value R.

If -r is not used, every node is at its optimal depth,
-r 0 will trade depth on non-critical paths for a smaller area (the LUT network still has an optimal depth),
-r R will allow depth to increase by at most R (then dfmap is called to reduce the area).
-s  specifies the cone input size S for which resynthesis of cones are performed for a smaller LUT network depth.


* turbomap [ -k <K_value> ] [-c <clock period> ] [ -a <mode> ]

 
Map a K-bounded network into a K-LUT network with retiming for clock period minimization.

-k specifies the LUT input size K, with default value of 5.

-c specifies an upper-bound on the minimum clock period, -1 means no specific upper-bound

-a specifies whether to perform area reduction on the mapping with retiming solution

1: consider label relaxation, better results with longer runtime
2: no label relaxation, recommended mode


* dfmap [ -k <K_value> ]
 

Map a K-bounded network into a K-LUT network of optimal area WITHOUT any node duplication.
It is used after flowmap -r and mffc_shrink, and is followed by an LUT packing procedure. For example, we use dfmap in
"flowmap -k 5 -r 1; mffc_shrink -k 5; dfmap -k 5; greedy_pack -k 5; "
-k  specifies the LUT input size K, with a default value 5.


* cutmap [ -k <K_value> ] [-x ]
 

Map a K-bounded network into a K-LUT network of optimal depth with simultaneous area minimization.
Area can be further reduced by post-processing packing routines.

-k  specifies the LUT input size K, with a default value 5.

-x  specifies depth relaxation on non-critical paths.
 

* zmap [ -k <K_value> ] [-c ]
 
Map a K-bounded network into a K-LUT network of optimal depth with simultaneous area minimization (cut enumeration approach).
Area can be further reduced by post-processing packing routines.

-k  specifies the LUT input size K, with a default value 5.

-c  will minimize area with no bound on depth
 

* eab_pack -f eab_config_filename [-o output_file_name]
 
eab_pack is a post-mapping EMB Packing procedure, which takes the mapped network as the input and group as many LUTs as possible into EMBs based on the concepts of MFFC and MFFS. The primary objective of eab_pack is to minimize the circuit area with EMBs, while the second goal maintains the mapped circuit delay which results in the maintainence of the layout delay. The second objective is achieved based on the slack computation and delay checking whenever an MFFS is ready to be used as EMB implementation.

-f eab_config_filename  Take the configuration file specified by eab_config_filename. The format of this config file can be referred to the file named .eab_pack_config.

-o output_file_name  Write the output eqn enhanced file (with EMB implementation information as the comment) to the file specified by output_file_name. If not specified, the output will go to the file named sisout.eab.
 

* eab_premap -f eab_config_filename [-o output_file_name]
 
eab_premap is a pre-mapping EMB Packing procedure, which takes the unmapped network as the input and group as many gates as possible into EMBs based on the concepts of MFFC and MFFS. The primary objective of eab_premap is to minimize the circuit area with EMBs, while the second goal maintains the pseudo-optimal (optimal in practice) circuit delay which results in the maintainence of the layout delay with the following delay optimal technology mapping. The second objective is achieved based on the slack computation and delay checking whenever an MFFS is ready to be used as EMB implementation.


* hetero_map -f hetero_map_config_filename
 

hetero_map is a delay optimal technology mapping algorithm for heterogeneous FPGAs, where there are LUTs with different sizes. Given a K1 bounded network (k1 is the smallesat LUT size), HeteroMap will compute the mapped network of minimum delay with heterogeneous LUTs.

-f hetero_map_config_filename  Take the configuration file specified by hetero_map_config_filename. The format of this config file can be referred to the file named .hetero_map_config.
 

* hm_fm_bs -f hm_fm_bs_config_filename
 
hm_fm_bs (BinaryHM) is an EMB mapping procedure. The primary objective of hm_fm_bs is to minimize the circuit delay with EMBs.

-f hm_fm_bs_config_filename  Take the configuration file specified by hm_fm_bs_config_filename. The format of this config file can be referred to the file named .hmfmbs_config.
 

* hf_cr_bs -f hf_cr_bs_config_filename
 
hf_cr_bs (CN-HM) is an EMB mapping procedure. The primary objective of hf_cr_bs is to minimize the circuit delay with EMBs.

-f hf_cr_bs_config_filename  Take the configuration file specified by hf_cr_bs_config_filename. The format of this config file can be referred to the file named .hfcrbs_config.
 

* praetor [ -k <K_value> ] [ -t <Max_cuts> ] [ -o <opti_goal> ] [ -u <duplication_feature> ]

Map a K-bounded network into a K-LUT network with minimized area. It runs very fast and provides better area-oriented solutions than previous published algorithms.

-k specifies the LUT input size K, with a default value 5.

-t specifies the maximum number of cuts allowed for each node, with default value as infinity.

-o specifies the optimization goal. 1: area+delay, 2: delay+area. Default is area only.

-u specifies mapping method. No duplication allowed without this parameter. With this parameter, 1: duplication, 2: two phase mapping.
 

* plamap BLIF_Input PLA_In PLA_PTerm PLA_Out [Cluster_Fanout_Threshold] [PTerm_Threshold] [Depth_Relax]

Map a network with name <BLIF_Input> into a CPLD consisting of PLAs. Each PLA has <PLA_In> inputs, <PLA_PTerm> product terms, and <PLA_Out> outputs. The PLA is specified as (In-PTerm-Out)PLA. plamap is performance-driven and provides area-delay tradeoff features.

Cluster_Fanout_Threshold: delay/area tradeoff for small PLA. Set as c x PLA_Out. Default c=3, e.g., Cluster_Fanout_Threshold=12 for (10-12-4)PLA.

PTerm_Threshold: delay/area tradeoff for PLA with PLA_In >= 30. Set as 20~30. Default PTerm_Threshold=20, e.g., 20 for (36-80-16)PLA.

Depth_Relax: relax circuit mapping depth to improve area. Set as 0 or 1. Default Depth_Relax=0, which offers better delay. 1 offers better area with depth increased by 1.
 

* daomap [ -k <K_value> ]
 
Map a K-bounded network into a K-LUT network of optimal depth with simultaneous area minimization (cut enumeration approach). This is the latest mapping algorithm released from the group.

-k  specifies the LUT input size K, with a default value 4.


 

4. Multi-output CLB Matching

* match_two [ -l ] [ -r ] [ -c ] [-w ] [-v | -f ]
 
Compute the best matching on an LUT network, which gives a two-output CLB mapping solution.
Each pair will contain a "left LUT" of size left_lut_size and a "right LUT" f size right_lut_size,
which can be put into the same CLB of size = combined_clb_size. Unpaired singletons are CLBs with unused left or right LUT.

It is possible that instead of the maximum cardinality matching, a weighted matching is computed to reflect certain considerations in pairing up theLUTs (e.g. routability, etc.). Currently, a simple weight function

w(u, v) = computed_weight(u, v) + nominal_weight
is used, where the "nominal weight" is actually a "non-weight" factor to tune down the weighting factor.
a parameter w specifying the "percentage" of nominal weight can be supplied. by changing w (0<=w<=100),
the significance of the weight can be changed. with w=100, maximum cardinality matching is guaranteed and weight is only used to break ties.
with w=0, cardinality is completely ignored. if w is not specified, normal cardinality matchingis carried out (note this may be different from w=0), which is faster.

when verbose mode (-v or -f) is selected, the list of CLBs will be printed.
There are three types of CLBs:
(1) full CLB with 2 LUTs, in the format ( Left_LUT , Right_LUT )
(2) half-full CLB with one LUT, in the form ( Left_LUT , () ) or ( () , Right_LUT )
(3) single LUT CLB, in the form of ( LUT )
 
-l input size limit of left LUT. default 4.
 
-r input size limit of right LUT. default 4.
 
-c input size limit of the CLB. default 5. this is the fanin limit of an unmatched LUT.
 
-w the percentage of added nominal weight.

default is off (i.e. no weight is considered). allowed value 0 to 100.

 
-v verbose output matching list to standard output.
default is silent output (i.e. only CLB count).

 
-f verbose output matching list to file.
 
Note that the default set reflects mapping for Xilinx XC3000 series CLBs, where paired LUTs usually share up to 3 inputs, so weight can be turned off.
For Xilinx XC4000 series CLBs, use -l 4 -r 4 -c 8 -w xx and decrease xx if you encounter routing problem (or use 'match_4k' for probably better result).

 
 
 

5. Net-Delay Data Access


 
* fl_delay { -i [ <file> ] | -o [ <file> ] | -p [ -v ] }

Access net-delay data when network is mapped under net-delay model.
the delay file has the following format: <network_name> <netowrk_size> <pi_delay> <po_delay> <lut_delay> <node_name> <node_fanout_net_delay> <node_name> <node_fanout_net_delay> ... ... ... ... <node_name> <node_fanout_net_delay>
(i.e. whitespace is used as field separator, and no comment, redefinable separator, empty lines, etc. are supported.)
note that PO nodes are attached when the network is loaded, they are not included (a PO node does not have fanout anyway).
 
-i [ <file> ] read delay values from <file> and assign
to each net. if no <file> parameter, the default is <network_name>.dly. ***

 
-o [ <file> ] write net-delay values to <file>. default is <network_name>.dly. ***
 
-p [ -v ] print out the overall delay of the network.
with -v option, a critical path will also be printed. ***

 
command "fl_delay -o|-p" assumes that the delay values are properly assigned to nodes(nets).
If this is not true, the result can be meaningless. "fl_delay -i" requires that the name of network and the nodes are matched strictly.
it's a good approach to use "fl_delay -o" to get a template for the delay data file.

 
 

6. Post-Processing Commands

 
* mpack [ -k <K_value> ] [ -m ] [ -p | -g ]
 
Reduce the number of nodes in the K-bounded network through predecessor packing and/or gate decomposition.
(Each node is regarded as an LUT).

-k  specifies the LUT input size K, with a default value 5.

-m  enable collapsing into multiple fanouts (for better results)

-p  predecessor packing only, no gate decomposition.

-g  gate decomposition only, no predecessor packing.


* greedy_pack [ -k <K_value> ] [ -m ] [ -p | -g ]
 

Same as mpack, but with a fast graph matching heuristics.


* mppack = mpack -p

* greedy_ppack = greedy_pack -p

* flowpack [ -k <K_value> ]
 

Pack LUTs together when possible for reducing area.

-k  specifies the LUT input size K, with a default value 5.


 
 

7. Printing Commands

* fl_print_mffc [ -v ]

Print MFFC decomposition of the network. -v option will print the root,
members, size, and fanin size of each MFFC; without -v the members are
not printed. Printing format is bad (sorry).
 
fl_nstatus [ -d ] [ -s | -v ]

Print network status. With -d option non-unit delay model is assumed; the
net delay values must have been properly attached to obtain meaningful
results. by default unit delay model is assumed. Will print #inputs, #output,
#nodes, overall delay, and I/O size statistics for the network. With -s
option, I/O status will include the count of nodes for each fanin and fanout
size. With -v option, in addition to the effect of -s option, for each node
the name, indegree, outdegree, slack (w.r.t the overall network delay),
fanin and fanout nodes are also printed (this format is usually hard
to read on screen; better redirect to a file).

 
 

8. Programmable Logic Block Generation Commands

 
* match_3k [ { -v | -f <outfile> } ] [ -e ]
 
Pair up 4-LUTs for XC3000 CLBs and print pairing results.
(Two 4-LUTs with 3 common inputs can be put in one CLB.)
The network is not changed.

-v  print the CLB output(s) to standard output

-f  print the CLB output(s) to <outfile>

-e  also print LUT network functions in EQN format
 

* match_4k [ { -v | -f <outfile> } ] [-h <threshold> ]
 
Group up LUTs for XC4000 CLBs and print grouping results.
(If a 5-LUT is decomposed properly, it might be possible to be packed with another 4-LUT into one CLB.)
The network is not changed.

-v  print LUT grouping results and LUT network functions to standard output

-f  print LUT grouping results and LUT network functions to <outfile>

-h  employ fast 4-LUT pairing heuristics when the number of 4-LUTs is more than <threshold> in the LUT network

9. Utility Commands

 
* mffc_shrink [ -k <K_value> ]
 
Collapse MFFCs (with no more than K inputs) into a single node.
This is a pre-processing step of dfmap for improving dfmap results.

-k  specifies MFFC input size K, with a default value 5.
 

* fl_nstatus [ -s ]
 
Print network information (number of PIs, POs, levels, nodes, etc.).

-s  also print node fanin/fanout distributions
 

* prn [ -m ]
 
Print network information (number of PIs, POs, levels, nodes, etc.).

-m  also print statistics on the MFFCs of the network


 
 
 

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Feedbacks and Bug Reports

Although the package has gone through a number of tests, the authors do not guarantee the correctness of the programs. Bug fixes will be distributed to users when applicable. Suggestions, comments, and bug reports, are welcome and should be sent to one of the developers at demingc@cs.ucla.edu.

 
 
 

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Last updated by WebMaster on 7/14/2004