RASP

FPGA/CPLD Technology Mapping and Synthesis Package

Project Director:  Prof. Jason Cong

Authors: Deming Chen, Eugene Ding, Zhijun Huang, Yean-Yow Hwang, John Peck, Chang Wu, Songjie Xu

Copyright (C) 1991-2004 the Regents of University of California
 

RASP, an FPGA/CPLD technology mapping and synthesis package, is the synthesis core of the UCLA RASP System developed at UCLA VLSI CAD LAB. This site is actively updated.
 
 
 



 
Download the RASP Technology Mapping Limited Source Package (Solaris only) Version B1.1
Download the RASP Technology Mapping Executable Package (Solaris and Linux versions available) Version B2.1
Acknowledgement and Contact Info
Package Content
Technical References
Usage
Feedbacks and Bug Reports

 
 
 

 

RASP source release B 1.1 + PLAmap B 1.0

This limited source release includes the following mapping algorithms:


Download the RASP Technology Mapping Limited Source Package

Download the RASP Technology Limited Source Package (Solaris only. Use a browser from Unix.)
 
 
 



 

RASP executable release B 2.1

This executable release includes the following mapping algorithms:


Download the RASP Technology Mapping Executable Package

Download the RASP Technology Mapping Executable Package (Solaris and Linux versions available. Use a browser from Unix or Linux.)
 
 
 



 

ACKNOWLEDGEMENT


 
 
 

 

PACKAGE CONTENT


 
 
 

 

TECHNICAL REFERENCES

    J. Cong, and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.

    J. Cong, and Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol 2., No. 2, June 1994, pp. 137-148.

    J. Cong, Y. Ding, T. Gao, and K. Chen, "LUT-Based FPGA Technology Mapping under Arbitrary Net-Delay Models," Computers & Graphics , Vol.18, No.4, 1994, 507-516.

    J. Cong, and Y. Ding, "Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs," Proc. 1993 IEEE/ACM Int'l Conf. on CAD, Santa Clara, CA, Nov. 1993, pp. 110-114.

    K.Chen, J.Cong, Y.Ding, A.Kahng, and P.Trajmar, "DAG-MAP: Graph-Based FPGA Technology Mapping for Delay Optimization," IEEE Design & Test of Computers, Sept. 1992

    J. Cong, J. Peck, and Y. Ding, "RASP: A General Logic Synthesis System for SRAM-based FPGAs," Proc. ACM 4th Int'l Symp. on FPGA, pp. 137-143, 1996

    J. Cong, and Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping," Proc. ACM 3rd Int'l Symp. on FPGA, Feb. 1995, pp. 68-74.

    J. Cong, and Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rd Design Automation Conf., pp. 726-729, 1996.

    J. Cong, and C. Wu, "An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design", Proc. IEEE Int'l Conf. on Computer Design, Austin, Texas, Oct. 1996, pp. 572-578.

    J. Cong, and Y. Hwang, "Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping"Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, CA., Feb. 1997, pp. 35-42.

    J. Cong, and C. Wu, "FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits" Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, CA., June 1997, pp. 644-649

    J. Cong, and S. Xu, "Technology Mapping for FPGAs with Embedded Memory Blocks" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 179-188

    J. Cong, and Y. Hwang, "Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 27-34

    J. Cong, and C. Wu, "Optimal FPGA Mapping and Retiming with Efficient Initial State Computation"Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 330-335

    J. Cong, and S. Xu, "Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs" Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 704-707

    J. Cong, and S. Xu, "Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources"Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1998, pp. 40-45.

    J. Cong, and C. Wu, "An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming" IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems vol 17, no 9, 1998, pp. 738-748

    J. Cong, and Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology in LUT-based FPGA Designs" TODAES , vol 5, no 3, July 2000.

    J. Cong, C. Wu, and E. Ding, "Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution" Proc. ACM Intl. Symp. on FPGA Monterey, California, pp. 29-35, February 1999.

    D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architecture" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,, vol. 22, no. 10, pp. 1424-1431, October 2003

    D. Chen, and J. Cong, "DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs," Proc. IEEE International Conference on Computer Aided Design, San Jose, California, November 2004.


 
 
 

 

USAGE