The TRIO package includes the following optimization engines:
There are two types of models to compute the device delay. One is the simple device model based on
There are also two types of interconnect capacitance models. One is the simple capacitance model based on
There are two types of device sizing formulations. One is the continuous gate sizing formulation, where the driver/buffer is characterized by one size under the assumption that the ratio between p- and n-transistors within a driver/buffer are fixed. All engines support the gate sizing formulation. In addition to the gate sizing formulation, stis1 and stis2 also supports transistor sizing formulation, i.e., the size of each transistor is assigned independently.
Algorithms in TRIO can be classified into two categories: local/bound refinement based approach and bottom-up dynamic programming based approach.
Engine siss, giss, stis1 and stis2 use local/bound refinement based approach. Engine bisws and batree use bottom-up dynamic programming based approach.
Wiresizing optimization was proposed in Ref using local refinement (LR) operation. Ref operation that may be 100x faster than the LR operation.
Simultaneous driver/buffer and wire sizing for a single net was proposed in Ref using alternated wire sizing and device sizing procedures, where wire sizing is based on the BLR operation and device sizing is based on closed-form formula.
Simultaneous transistor and interconnect sizing was proposed in Ref and Ref for multiple nets. Engine stis1 does not consider wire spacing, whereas stis2 considers the wire sizing and spacing formulation. stis1 uses the simple model for interconnect capacitance, whereas stis2 used the table-based model for interconnect capacitance. Both use LR operation to compute device sizing under the simple model, or extended local refinement (ELR) Ref and Ref for bisws algorithm, and Ref for batree algorithm. In addition, algorithm concerning siss can be found in Ref.
Go back to the beginning