TRIO release B 1.0

Package Content

Project Director:    Prof. Jason Cong
Copyright (C) 1993-1998 the Regents of University of California

The TRIO package includes the following optimization engines:

wire sizing optimization
single-net interconnect sizing and spacing considering coupling capacitance from its neighboring nets
global interconnect sizing and spacing considering coupling capacitance for multiple nets
simultaneous buffer and wire sizing
simultaneous transistor sizing and wire sizing using table-based model for device delay
simultaneous transistor sizing, and wire sizing and spacing using table-based models for device delay and coupling capacitance for multiple nets
buffer insertion, sizing and wire sizing
wiresized buffered A-Tree

There are two types of models to compute the device delay. One is the simple device model based on

(Intrinsic_delay + Output_resistance / Size * C_load)
where Intrinsic_delay is a constant and Output_resistance is the output resistance for a unit-size device. The other is the table-based device model which computes the device delay as a function of input waveform slope, device size and output load.

There are also two types of interconnect capacitance models. One is the simple capacitance model based on

(Unit_area_capacitance * width + Unit_fringe_capacitance)*Length.
where Unit_area_capacitance and Unit_fringe_capacitance are constants. The other is the table-based capacitance model, which considers area, fringe and coupling capacitance as functions of wire width and spacing Ref[4].

There are two types of device sizing formulations. One is the continuous gate sizing formulation, where the driver/buffer is characterized by one size under the assumption that the ratio between p- and n-transistors within a driver/buffer are fixed. All engines support the gate sizing formulation. In addition to the gate sizing formulation, stis1 and stis2 also supports transistor sizing formulation, i.e., the size of each transistor is assigned independently.

Algorithms in TRIO can be classified into two categories: local/bound refinement based approach and bottom-up dynamic programming based approach.

Engine wiresize, siss, giss, sbws, stis1 and stis2 use local/bound refinement based approach. Engine bisws and batree use bottom-up dynamic programming based approach.

Wiresizing optimization was proposed in Ref[8] using local refinement (LR) operation. Engine wiresize implements bundled local refinement (BLR) Ref[1] operation that may be 100x faster than the LR operation. It uses the simple model for the interconnect capacitance.

Simultaneous driver/buffer and wire sizing for a single net was proposed in Ref[7] using alternated wire sizing and device sizing procedures, where wire sizing is based on the BLR operation and device sizing is based on closed-form formula. Engine sbws implements iterative LR and BLR operations (LR for devices and BLR for wires) proposed in Ref[2] and Ref[3] . It uses the simple model for both device delay and interconnect capacitance.

Simultaneous transistor and interconnect sizing was proposed in Ref[2] and Ref[3] for multiple nets. Engine stis1 does not consider wire spacing, whereas stis2 considers the wire sizing and spacing formulation. stis1 uses the simple model for interconnect capacitance, whereas stis2 used the table-based model for interconnect capacitance. Both use LR operation to compute device sizing under the simple model, or extended local refinement (ELR) Ref[9] and Ref[11] for bisws algorithm, and Ref[10] for batree algorithm. In addition, algorithm concerning siss can be found in Ref[5].

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