Synthesis and Optimization under Physical Hierarchy


This project investigates novel synthesis algorithms under a given physical hierarchy for early interconnect planning in nanometer technologies.
People
Project Director
 Professor Jason Cong
Students
  • Chin-Chih Chang
  • Yiping Fan
  • Ashok Jagannathan
  • Yizhou Lin
  • Xin Yuan
  • Zhiru Zhang
  • Michail Romesis
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    Software
    1. mGP: http://cadlab.cs.ucla.edu/mGP
    2. MCAS: http://cadlab.cs.ucla.edu/software_release/mcas/mcas-dw.htm
    3. MEVA: http://cadlab.cs.ucla.edu/arch/meva.htm
    Publications
    1. C.-C. Chang, J. Cong, Z. Pan, and X. Yuan, "Physical Hierarchy Generation with Routing Congestion and Control ", In Proc. International Symposium on Physical Design, pp. 36-41, Apr. 2002.
    2. J. Cong, "Timing Closure Based on Physical Hierarchy ", In Proc. International Symposium on Physical Design, pp. 170-174, Apr. 2002.
    3. J. Cong and X. Yuan, "Multi-level Placement for Large-Scale Mixed-Size IC Designs ", In Proc. Asia South Pacific Design Automation Conference, pp. 325-330, Jan. 2003.
    4. J. Y. Lin, A. Jagannathan, and J. Cong, "Placement Driven Technology mapping for LUT-based FPGAs ", International Symposium on Field Programmable Gate Arrays, pp. 121-126, Feb. 2003.
    5. C.-C. Chang, J. Cong, Z. Pan, and X. Yuan, "Multilevel Global Placement with Congestion Control", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22(4), pp. 395-409, Apr. 2003.
    6. J. Cong, A. Jagannathan, G. Reinman, and M. Romesis, "Microarchitecture Evaluation with Physical Planning", In Proc. ACM/SIGDA Proceedings of the 40th Design Automation Conference, pp. 32-35, Jun. 2003.
    7. J. Cong and X. Yuan, "Multilevel Global Placement with Retiming", In Proc. ACM/SIGDA Proceedings of the 40th Design Automation Conference, pp. 208-213, Jun. 2003.
    8. J. Cong, Y. Fan, G. Han X. Yang, and Z. Zhang, "Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication", In Proc. International Conference on Computer Aided Design, pp. 536-543, Nov. 2003.
    9. J. Cong, T. Kong, J. Shinnerl, M. Xie, and X. Yuan, "Large-Scale Circuit Placement: Gap and Promise", In Proc. International Conference on Computer Aided Design, pp. 883-890, Nov. 2003.
    10. J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang, "Architecture and Synthesis for On-Chip Multicycle Communication", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23(4), pp.550-564, Apr. 2004.
    11. A. Jagannathan, H. Yang, K. Konigsfeld, D. Milliron, M. Mohan, M. Romesis, G. Reinman, and J. Cong, "Micro-Architecture Evaluation and Optimization with Interconnect Pipelining", In Proc. of the Asia South Pacific Design Automation Conference, pp. 8-15, Jan. 2005.
    12. J. Cong, M. Romesis, and J. Shinnerl, "Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning", In Proc. of the Asia South Pacific Design Automation Conference, pp. 1119-1122, Jan. 2005.
    Sponsors

    Copyright  2004.  The Regents of the University of California.