Bin Liu

I am a graduate student in computer science department, university of California, Los Angeles. My advisor is Prof. Jason Cong. Before coming to UCLA, I got M.Eng and B.Eng degrees from department of computer science and technology in Tsinghua University, Beijing, China.

Research

My research focuses on tecniques for behavioral/architectural synthesis in IC design, compiler transformations, and low-power design. I currently maintain the xPilot behavioral synthesis system.

Previously, I worked on algorithms for VLSI layout and low-power design.

Publications

• J. Cong, B. Liu and J. Xu. Coordinated resource optimization in behavioral synthesis. DATE'10.
• J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou. Accelerating Monte Carlo based SSTA using FPGA. FPGA'10.
• J. Cong, B. Liu and Z. Zhang. Scheduling with soft constraints. ICCAD'09, (Best paper award nomination).
• J. Cong, W. Jiang, B. Liu and Y. Zou. Automatic memory partitioning and scheduling for throughput and power optimization. ICCAD'09.
• J. Cong, A. Liu and B. Liu. A variation-tolerant scheduler for better than worst-case behavioral synthsis. ISSS/CODES'09.
• J. Cong, B. Liu and Z. Zhang. Behavior-level observability don't-cares and application to low-power behavioral synthesis. ISLPED'09.
• J. Cong, K. Gururaj, B. Liu, C. Liu, Z. Zhang, S. Zhou and Y. Zou. Evaluation of static analysis techniques for fixed-point precision optimization. FCCM'09.
• J. Cong, K. Gururaj, B. Liu, C. Liu, Y. Zou, Z. Zhang and S. Zhou. Revisiting bitwidth optimization. FPGA'09.

Some earlier ones.

• Y. Cai, B. Liu, J. Shi, Q. Zhou and X. Hong. Power delivery aware floorplanning for voltage island designs. ISQED'07.
• B. Liu, Y. Cai, Q. Zhou and X. Hong. Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-Vdd designs. ASPDAC'06.
• Y. Cai, B. Liu, Q. Zhou and X. Hong. A two-step heuristic algorithm for minimum- crosstalk routing resource assignment. IEEE Trans. CAS-II, 53(10):1007-1011.
• Y. Cai, B. Liu, Q. Zhou and X. Hong. A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design. PATMOS'05.

Contact Me

4651 Boelter Hall, UCLA
Los Angeles, CA 90095

Other

Well, this is still under construction. Let me think about what to put here.

Last update: 12/29/2009