MODELING AND DESIGN OF HIGH-SPEED VLSI INTERCONNECTS
Instructor: Prof. Jason Cong

COURSE DESCRIPTION

Detailed study of various problems in modeling and design of high-speed VLSI interconnect at both IC and packaging levels, including device and interconnect modeling, interconnect topology optimization for delay minimization, wiresizing and device sizing for both delay and performance optimization, and clock network design for high-performance systems.

OBJECTIVES OF THE COURSE

Present a board survey of the problems in modeling and design of high-performance VLSI interconnect and the state of art solutions. Provide necessary background for graduate students to carry out research in this area.

PREREQUISITES

CS 258A and 258F, or consent of instructor.

TEXTBOOKS

H. B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley Publishing Company, 1990. (required)
Selected research papers from the literature (Proc. of ACM/IEEE Design Automation Conference, Proc. IEEE Intl. Conf. on Computer-Aided Design, and IEEE Trans. on CAD)

GRADING POLICY

30% homework, 30% presentation, and 40% term paper.

COURSE OUTLINE

Week 1: Overview and Introduction.
Week 2: Modeling of VLSI Interconnects.
Week 3: Modeling of VLSI Interconnects (Cont'd).
Week 4: Modeling of VLSI Devices.
Week 5: Delay Budgeting and Timing-Driven Placement
Week 6: Interconnect Topology Optimization
Week 7: Device Sizing and Wiresizing
Week 8: Simultaneous Topology Optimization, Buffer Insertion, Buffer and Wire Sizing
Week 9: Clock Network Design
Week 10: Student Presentations on selected topics