Rapid scaling of IC technologies enables very high-degree of on-chip integration. It will soon be feasible to integrate a complex electronic system onto a single chip, including possibly microprocessors, embedded memories, programmable logics, and various application-specific circuit components designed by multiple teams for multiple projects. Such a system-on-a-chip may have significant advantages in performance, power consumption, volume, weight, and overall cost. However, there is no proven design methodology and no available design tools to support such giga-scale system-on-a-chip (SOC) integration. Many key questions related to SOC designs need to be answered, such as how to provide sufficient design abstraction which takes into consideration of the electrical details in nanometer designs (interconnect delay, noise, etc.), how to represent and characterize re-usable blocks (intellectual properties) so that they can be used from one technology generation to another, from one foundry to another, or even from one design environment to another, how to model the interaction of various heterogeneous functional blocks in a SOC for overall system-level simulation and optimization, how to certify "known-good designs" under both functional specification and performance constraints, etc..

This international workshop, to be jointly sponsored the National Science Foundation of US and the National Science Council of Taiwan, is intended to understand the challenges and critical research needs of design and verification technologies for giga-scale system-on-a-chip (SOC) integration in nanometer technologies and identify promising opportunities for innovation. The participation of researchers and engineers in Taiwan under the support of Taiwan National Science Council is important to the success of the workshop, as Taiwan now has a significant percentage of the world's largest and most advanced integrated circuit fabrication facilities. In the system-on-a-chip design era, system integration happens at fabrication foundries during IC manufacturing as opposed to in system houses through PCB board designs as in the past.

The driving force behind the spectacular advancement of the integrated circuit technology in the past thirty years has been the exponential scaling of the feature size, i.e., the minimum dimension of a transistor. It has been following the Moore's Law at the rate of a factor of 0.7 reduction every three years. It is expected that such exponential scaling will continue for at least another 10-12 years as projected in the recently published 1997 National Technology Roadmap for Semiconductors (NTRS'97). This will lead to over half a billion transistors integrated on a single chip with an operating frequency of 2-3 GHz in the 70nm technology by Year 2009. To sustain such an exponential growth to achieve giga-scale integration, however, requires a great deal of innovations in the design and verification technologies, in terms of both steady incremental extension of the existing design and verification capabilities and the revolutionary development of new design and verification paradigm and methodologies. For example, the recent study by SEMATECH showed that although the level of on-chip integration, expressed in transistors per chip, increases at an approximately 58% per year compound growth rate, the design productivity, measured in transistors per person-month, grows only at a 21% per year compound rate. Such a mismatch of silicon capacity and design productivity, if not resolved timely, will seriously limit the potential of achieving high-degree on-chip integration. On the other hand, many new challenges associated with giga-scale integration in nanometer technologies, such as lack of high level design abstraction due to the increasing importance of interconnect performance and reliability, lack of adequate methodology for design reuse, difficulties in integrating and interfacing heterogeneous systems on a single IC, rapid growing design and verification complexity, etc., prevent us from improving design productivity, unless signification progress and innovation is made in design and verification technologies.

The objective of this workshop is to understand the challenges and critical research needs of design and verification technologies for giga-scale SOC integration in nanometer technologies and identify promising opportunities for innovation. The next two subsections discuss some of the challenges and needs for innovation in the design technologies and verification technologies, respectively, which will be used as the 'seed topics' for discussion at the workshop. We expect more broad and in-depth contributions from workshop attendees on these topics.

Challenges and Opportunities in Design Technologies

One effective approach to designing a complex system is to provide various levels of abstraction and enables the designer to carry out the design at the high level and successively refine the design into lower level implementations. The development of register-transfer level (RTL) synthesis capability in 1980's is critical for us to reach today's design complexity and design productivity. However, the current design methodologies are facing many difficulties and new challenges for large-scale on-chip system integration in nanometer designs due to the following reasons.

The current flow goes through behavior level design, RTL level design, logic design, and physical design. The success of such an approach depends heavily on the good correlation between the abstract model at each level and its physical implementation in the final design. Such a correlation, however, becomes very difficult to maintain, as the existing abstractions are incapable of modeling the performance, reliability, and complexity of the interconnects, which in fact have become the dominating factors to be considered and optimized in nanometer designs. The rapid scaling of IC technology leads to much smaller and faster devices, but more resistive interconnects with larger coupling capacitance. As a result, interconnects may contribute to over 70\% of the overall system performance. They also become very noisy in high-performance designs in nanometer technologies due to capacitive and inductive coupling noise and power and ground bounce. However, the current design representation and design abstraction methodologies do not provide a sufficient way to model, represent, predict, and control interconnect performance and reliability for high performance designs in nanometer technologies.

The hierarchical design methodology is also widely used nowadays to design complex systems, which applies the divide-and-conquer methodology to decompose the large system into a set of smaller subsystems recursively and carries out the design hierarchically. It is common to decompose a complex IC into a number of functional blocks, each of them designed by one or a team of engineers with manageable complexity, and then go through a full-chip assembly phase to interconnect these blocks together. Such hierarchical design methodology is also facing serious difficulty in nanometer designs. Although the functionality and structure of a circuit can usually be decomposed hierarchically, many performance and reliability related issues in nanometer designs, such as interconnect delay, crosstalk, power and ground bounces due to simultaneous switching, do not fit naturally into the function hierarchy. As a result, we are facing a methodology crisis with no adequate abstraction model and scalable methodology to handle the rapid growing design complexity.

Efficient reuse of existing designs and intellectual property will play an important role in reducing the mismatch between silicon capacity and design productivity. Efficient design reuse, however, also introduces new challenges to design abstraction and the hierarchical design methodology, as it requires proper representation, abstraction, and characterization of existing designs in terms of its functionality, performance, reliability, and possible interactions with the environment. It also requires a systematic approach to update the characterization and implementation of an existing design when we migrate from one technology generation to another, from one foundry to another, or even from one design environment to another. Such capabilities have yet to be developed and validated by the industry.

Therefore, an important topic of this workshop is to investigate new design styles and circuit fabrics with predictable performance and identify new design techniques and methodologies to (i) enable SOC designs with high level of abstraction yet predictable performance and (ii) support efficient design reuse. The objective is the reduce or eliminate unnecessary design iterations in the design process, reduce the total design time, and increase the overall design productivity to match the rapid increase of silicon capacity.

Another challenge for SOC design in nanometer technologies is the possibility and need to integrate heterogeneous subsystems of vastly different circuit characteristics and functionality in a single IC chip. Rapid increase of IC capacity makes it possible to integrate microprocessors, embedded memories, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), and various analog components into a single IC. As a result, future IC design will involve development of embedded operating systems, compilers for code-generation for embedded application softwares, software and hardware partition, co-design, and co-simulation, synthesis and layout of application-specific circuits, mapping and configuration of programmable logic, and many more. Analog components, such as A/D or D/A converters, RF transceiver circuits, and various sensors, may co-exist with digital components on the same chip. In this case, the interference between the digital and analog circuits, such as the noise from high-speed digital signals to low-level analog signals and electromagnetic interference (EMI) generated by the high-frequency circuits, needs to be properly modeled, analyzed, and considered by the design and test tools. The needs of integrating various design techniques and design tools developed for completely different design styles, automatically synthesizing of their interfaces, and optimizing the overall system performance and cost far exceed capability of today's design technology. Therefore, another objective of this workshop is to identify critical research needs and promising new design methodologies for mapping and implementing a complex applications to a set of heterogeneous subsystems with proper cost/performance trade-off, and efficiently synthesizing their interfaces, and reliably integrating them onto a single IC design.

Challenges and Opportunities in Verification Technologies

Traditional emphasis of design and CAD research has been on the synthesis process. However, it is more and more apparent that the verification process is getting increasing importance in system designs, especially SOC designs. We refer to verification in a broad sense so that the term encompass formal verification, functional debugging, simulation, and manufacturing testing. For example, functional debugging dominates both development time and cost in modern design process. The UltraSPARC design team from SUN Microsystems reported that debugging efforts (mainly architecture and functional verification) took two times longer than the design activities.

The key technological and application trends indicate that the cost and time of verification follow sharply ascending trajectories. The exponential increase of the on-chip device count due to IC technology scaling leads to rapid growth in the number of transistors per pin in each new generation of designs and an increasing level of hardware sharing due to increasing clock speeds. For example, the number of transistors per pin in 1994, 1996, and 1998 were 7,000, 14,000, and 29,000 according to Microprocessor Report data, indicating an exponential growth trend. This will make functional debugging and manufacturing testing significantly more difficult.

Another factor which will make formal verification and simulation of SOCs even more difficult is that in many emerging applications a large number of components will be simultaneously interacting. Therefore, all currently very successful divide-and-conquer-based formal verification and simulation techniques will not be applicable anymore.

It is important to note that verification and debugging of SOCs will be more challenging at both micro (e.g. transistor) and macro (e.g. register transfer and application) levels. At the micro level, the new problems are due to very high clocking rates and rapidly shrinking technologies; at the macro level due to bursty and unpredictable nature of applications.

Furthermore, reusability-based systems-on-chip of design is inherently associated with components where will be very difficult to add testing hardware without impact on timing and/or area. The designer of individual components - building blocks can not anticipate how system-on-chip designer will use the reusable components. For example, the component design does not not which pins will be accessible and which are not from the boundary of final SOC. In addition it is clear that different components will follow different test paradigms (e.g. BIST, or full scan or partial scan). Since the reusable components are aggressively optimized, any addition of test hardware will potentially result in area/performance/power degradation.

Finally, need for intellectual property protection (IPP) and security which implies that access to some parts of design (reusable components) will be partially (IPP-induced) or even fully (security: e.g. secrete key storage area) prevented. We will encounter a completely new set of testing. debugging and verification problems, related to IPP and security.

Therefore, this workshop intends to investigate the following verification topics:

• how to combine formal verification, simulation, emulation and prototyping for verification and debugging of system on silicon;
• the role of standards in SOC testing and debugging;
• new test (e.g. power ratio-based techniques) and debugging (e.g.laser reparation) technologies;
• fault modeling and simulation for deep submicron;
• development of test needs-aware parameterizable reusable components;
• the role of reconfigurable hardware for testing and performance evaluation;
• performance evaluation and modeling techniques for SOC;
• engineering-change techniques for functional fault fixing;
• interaction between IPP and security requirements and verification needs.

The workshop will also discuss several other issues related to giga-scale integration for system-on-a-chip designs, including, but not limited to

• implication on graduate education to meet giga-scale integration for system-on-a-chip challenges;
• collaborative design environment and infrastructure to facilitate research and development for giga-scale design and integration; and
• possible future US/Taiwan collaboration in research and education in the area of system-on-a-chip integration, ncluding the possibility of setting up an NSF-sponsored program on Summer Institute in Taiwan.

• 6-8pm: reception

• Morning:Invited talks and position statements from selected workshop attendees (open to the public)
• Afternoon: Visit to TSMC and presentations from TSMC on their view, approaches, and needs for SOC and IP integration
• Evening: Working dinner -- identify top-10 problems for design and verification technologies for SOC designs

• Morning:Partition into 3-4 working groups and group discussions to identify challenges and opportunities, and give recommendations
• Afternoon:
  • Discussion on implication of graduate education to meet giga-scale integration for system-on-a-chip and possible future US/Taiwan research/education collaboration in this area
  • Produce workshop report draft
• Evening: banquet, closing statements

Related documents and links

1. "EDA Roadmap Taskforce Report -- Design of Microprocessors"
   MS Word 1
   PDF 1

2. "Workshop Summary"
   

3. "Keynote Speech by D.F. Chan"
   

4. "Workshop Final Report"