Jason Cong's Publications

Books

  1. Liberskind-Hadas, R., N. Hasan, J. Cong, P. Mckinley and C. L. Liu, Fault Covering Problems in Reconfigurable VLSI Systems. Kluwer Academic Publishers, 1992.

  2. Cong, J., L. He, and C. K. Koh, Layout Optimization , Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet, NATO ASI Series, Kluwer Academic Publishers, 1997.

Journal Publications

  1. Cong, J., D. F. Wong and C. L. Liu, "A New Approach to Three- or Four-Layer Channel Routing". IEEE Trans. Computer-Aided Design, 1988, Vol. 7, pp. 1094-1104.

  2. Cong, J. and D. F. Wong, "Generating More Compactable Channel Routing Solutions". Integration: the VLSI Journal, April, 1990, Vol. 9, pp. 199-214.

  3. Cong, J. and C. L. Liu, "On the Over-the-Cell Channel Routing Problem," IEEE Trans. Computer-Aided Design, April, 1990, Vol. 9, pp. 408-418. (1992 IEEE CAS Outstanding Young Author Award Candidate)

  4. The, K. S., D. F. Wong and J. Cong, "A Layout Modification Approach to Via Minimization". IEEE Trans. on Computer-Aided Design, April 1991, Vol. 10, pp. 536-540.

  5. Cong, J. and C. L. Liu, "On the k-Layer Planar Subset and Topological Via Minimization Problems,"  IEEE Trans. on Computer-Aided Design, Aug. 1991, Vol. 10, pp. 972-981.

  6. Cong, J., "Pin Assignment with Global Routing for General Cell Design". IEEE Trans. on Computer-Aided Design, Nov. 1991, Vol. 10, pp. 1401-1412.

  7. Cong, J., A. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, "Provably Good Performance-Driven Global Routing". IEEE Trans. on Computer-Aided Design, June 1992, Vol. 11, No. 6, pp. 739-752.

  8. Chen, K. C., J. Cong, Y. Ding, A. Kahng, and P. Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization". IEEE Design & Test, Sept, 1992, pp. 7-20.

  9. Khoo, K. Y. and J. Cong, "A Fast Multilayer General Area Router for MCM Designs". IEEE Trans. on Circuits and Systems (Special Issue on Simulation, Modeling, and Electrical Design of High-Speed and High-Density Interconnects), Nov. 1992, pp. 841-851.

  10. Cong, J and B. Preas, "A New Algorithm for Standard Cell Global Routing". Integration: the VLSI Journal, Nov. 1992, Vol. 14, No. 1, pp. 49-65.

  11. Cong, J., M. Hossain and N. Sherwani, "A Provably Good Multilayer Topological Planar Routing Algorithm In IC Layout Designs". IEEE Trans. on Computer-Aided Design, Jan. 1993, pp. 70-78.

  12. Cong, J., B. Preas and C. L. Liu, "Physical Models and Efficient Algorithms for Over-the-Cell Routing in Standard Cell Designs". IEEE Trans. on Computer-Aided Design, May 1993, pp. 723-734.

  13. Cong, J., A. B. Kahng and G. Robins, "Matching-Based Methods for High-Performance Clock Routing". IEEE Trans. on Computer-Aided Design, Aug. 1993, Vol. 12, No. 8, pp. 1157-1169.

  14. Cong, J. and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs". IEEE Trans. on Computer-Aided Design, Jan. 1994, Vol. 13, No. 1, pp. 1-12. (1995 Circuit and System Society Best Paper Award in IEEE Transactions on CAD)

  15. D. Zhou, S. Su, F. Fsui, D. S Gao, and J. Cong, "A Simplified Synthesis of Transmission Lines with a Tree Structure". Journal of Analog Integrated Circuits and Signal Processing (Special Issue on High-Speed Interconnects), Jan. 1994, Vol. 5, No. 1, pp. 19-30.

  16. Cong, J. and Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, June 1994, Vol. 2, No. 2, pp. 137-148.

  17. Cong, J., Y. Ding, T. Gao and K. C. Chen, "LUT-Based FPGA Technology Mapping Under Arbitrary Net-Delay Model," Computers and Graphics, 1994, Vol. 18, No. 4, pp. 507-516.

  18. Cai, Y., D. F. Wong and J. Cong, "Channel Density Minimization by Pin Permutation". VLSI Design: An International Journal of Custom-Chip Design, Simulation, and Testing (Special Issue on Optimization in VLSI Synthesis and Layout), 1994, Vol. 2, No. 2, pp. 171-183.

  19. Alpert, C. J., J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, "On the Minimum Density Interconnection Tree Problem," VLSI Design: An International Journal of Custom-Chip Design, Simulation, and Testing (Special Issue on Optimization in VLSI Synthesis and Layout), 1994, Vol. 2, No. 2, pp. 171-183.

  20. Cong, J. and C. K. Koh, "Simultaneous Driver and Wire Sizing for Performance and Power Optimization". IEEE Trans. on VLSI Systems, Dec. 1994, pp. 408-425.

  21. Cong, J. and Y. Ding, "On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping". Integration: the VLSI Journal, Vol. 18, 1994, pp. 507-516.

  22. Cong, J. and K. S. Leung, "Optimal Wiresizing Under Elmore Delay Model". IEEE Trans. on Computer-Aided Design, Mar. 1995, pp. 321-336.

  23. Cong, J. and K. Y. Khoo, "An Efficient Multilayer MCM Router Based on Four-Via Routing". IEEE Trans. on Computer-Aided Design, Oct. 1995, pp. 1277-1290.

  24. Kleinrock, L., M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, and J. Bannister, "The Supercomputer Supernet: A Scalable Distributed Terabit Network", J. of High Speed Networks, Vol. 4, No. 4, 1995.

  25. Cong, J., W. J. Labio, and N. Shivkumar, "Multiway VLSI Circuit Partitioning Based on Dual net Representation". IEEE Trans. on Computer-Aided Design, April. 1996, pp. 396-409.

  26. Kleinrock, L., M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, J. Bannister, S. Monacos, T. Bujewski, P. C. Hu, B. Kannan, B. Kwan, E. Leonardi, J. Peck, P. Palnati, and S. Walton, "The Supercomputer Supernet Testbed: A WDM-Based Supercomputer Interconnect". J. of Lightwave Technology, Vol. 14, No. 6, June, 1996, pp. 1388-1399

  27. Cong, J. and Y. Ding "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays". ACM Trans. on Design Automation of Electronic Systems, Vol. 1, No. 2, April, 1996, pp. 145-204.

  28. Cong, J. and L. He "Optimal Wiresizing for Interconnects with Multiple Sources," ACM Transaction on Design Automation of Electronic Systems, Vol. 1, No. 4, Oct., 1996. pp. 478-511.

  29. Cong, J., L. He, C. K. Koh, ad P. Madden, "Performance Optimization of VLSI Interconnect Layout" Intergration, the VLSI Journal, Vol. 21, 1996, pp. 1-94.

  30. Lee, T. C. and J. Cong, "The New Line in IC Design", IEEE Spectrum, Mar. 1997, pp. 52-58.

  31. Cong, J. and P. Madden, "Performance-Driven Routing with Multiple Sources" , IEEE Trans. on Computer-Aided Design, Vol. 16, April. 1997, pp. 410-419.

  32. Cong, J., A. B. Kahng, C. K. Koh, and C.-W. Albert Tsao, "Bounded-Skew Clock and Steiner Routing", ACM Trans. on Design Automation of Electronic Systems, Vol. 3, 1998, pp. 341-388

  33. Cong, J., and C. Wu "An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming," IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems vol 17, no 9, 1998, pp. 738-748

  34. Cong, J., Kahng, A.B. and Kwok-Shing Leung, "Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17 (no. 1) Jan 1999. pp. 24-39

  35. Jason Cong and L. He "Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing,"  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, (no.4), IEEE, April 1999. pp. 406-420

  36. Chin-Chih Chang and J. Cong "An efficient approach to multilayer layer assignment with an application to via minimization",IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, (no. 5) May 1999. p.608-20

  37. Jason Cong and C. Wu "Optimal FPGA Mapping and Retiming with Efficient Initial State Computation," IEEE Trans. on Computer-Aided Design, November 1999, pp 1595 -1607

  38. J. Cong, J. Fang and K.Y. Khoo, "Via design rule consideration in multi-layer maze routing algorithms", IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, February 2000, pp 215-223

  39. Cong, J., and Y. Hwang "Structural Gate Decomposition for Depth-Optimal Technology in LUT-based FPGA Designs" ACM Trans. on Design Automation of Electronic Systems, vol 5, no 2, April 2000, pp. 193-225

  40. J. Cong and S. Xu, "Performance-Driven Technology Mapping for Heterogeneous FPGAs", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 19, no. 11, November 2000, pp 1268-1281

  41. J. Cong, "An Interconnect-Centric Design Flow for Nanometer Technologies,"  Proceedings of the IEEE, vol. 89, No. 4, April 2001, pp 505-528

Conference Publications

  1. Cong, J., D. F. Wong and C. L. Liu, "A New Approach to the Three Layer Channel Routing". Proc. Int'l Conf. Computer-Aided Design, Nov., 1987, pp. 378-381

  2. Cong, J. and D. F. Wong, "How to Obtain More Compactable Channel Routing Solutions". Proc. 25th IEEE/ACM Design Automation Conf., June, 1988, pp. 663-666.

  3. Cong, J. and C. L. Liu, "Over-the-Cell Channel Routing". Proc. Int'l Conf. Computer-Aided Design, Nov., 1988, pp. 80-83.

  4. Cong, J. and B. Preas, "A New Algorithm for Standard Cell Global Routing". Proc. Int'l Conf. on Computer-Aided Design, Nov., 1988, pp. 176-179. (Highlighted paper)

  5. Hasan, N., J. Cong and C. L. Liu, "A New Formulation of Yield Enhancement Problems for Reconfigurable Chips". Proc. Int'l Conf. Computer-Aided Design, Nov., 1988, pp. 520-523.

  6. Hasan, N., J. Cong and C. L. Liu, "A General Model for Fault Covering Problems in Reconfigurable Arrays". Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, 1988, pp. 319-326.

  7. The, K. S., D. F. Wong and J. Cong, "Via Minimization by Layout Modification". Proc. 26th ACM/IEEE Design Automation Conf., June, 1989, pp. 799-802.

  8. Hasan, N., J. Cong and C. L. Liu, "An Integer Linear Programming Approach to General Fault Covering Problems". Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 1989, pp. 146-156.

  9. Cong, J., "Pin Assignment with Global Routing". Proc. Int'l Conf. on Computer-Aided Design, Nov., 1989, pp. 302-305.

  10. Dong, S., J. Cong and C. L. Liu, "Constrained Floorplan Design for Flexible Blocks". Proc. Int'l Conf. on Computer-Aided Design, Nov., 1989, pp. 488-491.

  11. Cong, J. and C. L. Liu, "On the k-Layer Planar Subset and Via Minimization Problems". Proc. of European Design Automation Conf., March, 1990, pp. 459-463.

  12. Cong, J., B. Preas and C. L. Liu, "General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design". Proc. 27th ACM/IEEE Design Automation Conf., June, 1990, pp. 709-715.

  13. Kahng, A., J. Cong and G. Robins, "High-Performance Clock Routing Based on Recursive Geometric Matching". Proc. ACM/IEEE 28th Design Automation Conf., June 1991, pp. 322-327.

  14. Cong, J., A. Kahng and G. Robins, "Performance-Driven Global Routing for Cell Based IC's". Proc. IEEE Int'l Conference on Computer Design, Oct. 1991, pp. 170-173.

  15. Cong, J. and K. Khoo, "A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem". Proc. IEEE Int'l Conference on Computer Design, Oct. 1991, pp. 319-322.

  16. Cong, J., A. Kahng and G. Robins, "On Clock Routing for General Cell Layouts". Proc. IEEE 4th Int'l ASIC Conf., Sept. 1991, pp. 14-5.1 - 14-5.4.

  17. Cong, J., L. Hagen and A. Kahng, "Random Walks for Circuit Clustering". Proc. IEEE 4th Int'l ASIC Conf., Sept. 1991, pp. 14-2.1 - 14-2.4.

  18. Cong, J., A. Kahng, P. Trajmar, K. C. Chen, "Graph Based FPGA Technology Mapping for Delay Optimization". Proc. ACM Int'l Workshop on Field Programmable Gate Arrays, Feb. 1992, pp. 77-82.

  19. Cong, J., A. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, "Provably Good Algorithms Performance-Driven Global Routing". Proc. IEEE International Symposium on Circuits and Systems, May 1992, pp. 2240-2243.

  20. Cong, J., L. Hagen, and A. Kahng, "Net Partitions Yield Better Module Partitions". Proc. ACM/IEEE 29th Design Automation Conference, June 1992, pp. 47-52. (Best Paper Award Candidate)

  21. Chen, K. C. and J. Cong, "Maximal Reduction of Lookup-Table Based FPGAs". Proc. European Design Automation Conference, Sept. 1992, pp. 224-229.

  22. Khoo, K. Y. and J. Cong, "A Fast Multilayer General Area Router for MCM Designs". Proc. European Design Automation Conference, Sept 1992, pp. 292-297.

  23. Cong, J., Y. Ding, A. Kahng, P. Trajmar, and K. C. Chen, "An Improved Graph-Based FPGA Technology Mapping Algorithm For Delay Optimization". Proc. IEEE Int'l Conference on Computer Designs, Oct. 1992, pp. 154-158.

  24. Cong, J. and Y. Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs". Proc. IEEE Int'l Conference on Computer-Aided Design, Nov. 1992, pp. 48-53. (Highlighted paper)

  25. Boese, D., J. Cong, A. Kahng, K. S. Leung, and D. Zhou, "On High-Speed VLSI Interconnects: Analysis and Design". Proc. IEEE Asia-Pacific Conference on Circuits and Systems, Dec. 1992, pp. 35-40. (Invited paper)

  26. Khoo, K. Y. and J. Cong, "A Fast Four-Via Multilayer MCM Router". Proc. IEEE Multi-Chip Module Conf., March 1993, 179-184.

  27. Zhou, D., F. Tsui, J. Cong, and D. Gao, "A Distributive RCL-Model for MCM Layout". Proc. IEEE Multi-Chip Module Conf., March 1993, pp. 191-197.

  28. Iman, S., M. Pedram, C. Fabian, and J. Cong, "Finding Uni-Directional Cuts Based on Physical Partitioning and Logic Restructuring". 4th ACM/SIGDA Physical Design Workshop, April 1993, pp. 187-198.

  29. Alpert, C. J., J. Cong, A. B. Kahng, G. Robins, and M. Sarrafzadeh, "Minimum Density Interconnection Trees". Proc. IEEE Int'l Symp. on Circuits and Systems, May 1993, pp. 1865-1868.

  30. Cong, J. and Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping", Proc. ACM/IEEE 30th Design Automation Conference, June 1993, 213-218.

  31. Khoo, K. Y. and J. Cong, "An Efficient Multilayer MCM Router Based on Four-Via Routing", Proc. ACM/IEEE 30th Design Automation Conference, June 1993, 590-595.

  32. Cong, J., K. S. Leung, and D. Zhou, "Performance-Driven Interconnect Design Based on Distributed RC Delay Model", Proc. ACM/IEEE 30th Design Automation Conference, June 1993, 606-611.

  33. Cong, J. and M. Smith, "A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Designs", Proc. ACM/IEEE 30th Design Automation Conference, June 1993, 755-760.

  34. Cong, J. and Y. Ding, "An Optimal Performance-Driven Technology Mapping Algorithm For LUT-Based FPGAs Under Arbitrary Net-Delay Models", Proc. Int'l Conf. on Computer-Aided Design and Computer Graphics, Aug. 1993, pp. 599-604.

  35. Gao, T., K. C. Chen, J. Cong, Y. Ding, and C. L. Liu, "Placement and Placement Driven Technology Mapping for FPGA", Proc. IEEE ASIC Conf., Sept. 1993, pp. 91-94.

  36. Cong, J. and K. S. Leung, "Optimal Wiresizing Under the Distributed Elmore Delay Model", Proc. Int'l Conf. on Computer-Aided Design, Nov. 1993, pp. 110-114.

  37. Cong, J. and Y. Ding, "Beyond The Combinatorial Limit in Depth Minimization For LUT-Based FPGA Designs", Proc. Int'l Conf. on Computer-Aided Design, Nov. 1993, pp. 634-639.

  38. Cong, J., C. K. Koh, and K. S. Leung, "Wiresizing with Driver Sizing for Performance and Power Optimization", Proc. Int'l Workshop on Low Power Design, April 1994, pp. 81-86.

  39. Cong, J., Z. Li, and R. Bagrodia, "Acyclic Multi-Way Partitioning of Boolean Networks", Proc. 31st IEEE/ACM Design Automation Conf., June 1994, pp. 670-675.

  40. Cong, W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Netlist Representations", Proc. Int'l Conf. on Computer-Aided Design, Nov. 1994, pp. 56-62.

  41. Cong, J. and C. K. Koh, "Simultaneous Driver and Wire Sizing for Performance and Power Optimization", Proc. Int'l Conf. on Computer-Aided Design, Nov. 1994, pp. 206-212.

  42. Bagrodia, R., Z. Li, V. Jha, Y. Chen, and J. Cong, "Parallel Logic Level Simulation of VLSI Circuits", Proc. IEEE Winter Simulation Conf., Dec. 1994, pp. 1354-1361.

  43. Cong, J. and Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping", Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, Feb. 1995. pp. 68-74

  44. Cong, J. and Y. Ding, "On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping", Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, Feb. 1995. pp. 82-88

  45. Cong, J. and P. Madden, "Performance Driven Routing with Multiple Sources", Proc. Int'l Symp. on Circuits and Systems, Seatle, Washington, May 1995. pp. 203-206

  46. Cong, J. and C. K. Koh, "Minimum-Cost Bounded-Skew Clock Routing", Proc. Int'l Symp. on Circuits and Systems, Seatle, Washington, May 1995. pp. 215-218

  47. Cong, J. and Dongmin Xu, "Exploiting Signal Flow and Logic Dependency in Standard Cell Placement", Proc. Asia and South Pacific Design Automation Conf., Chiba, Japan, Aug. 1995, pp. 399-404.

  48. Cong, J., A. B. Kahng, C. K. Koh, and C. W. Tsao, "Bounded-Skew Clock and Steiner Routing Under Elmore Delay", Proc. ACM/IEEE Int'l Conf. on Computer-Aided Desgin, Santa Clara, CA., Nov. 1995, pp. 66-71.

  49. Cong, J. and Lei He, "Optimal Wiresizing for Interconnects with Multiple Sources", Proc. ACM/IEEE Int'l Conf. on Computer-Aided Desgin, Santa Clara, CA., Nov. 1995, pp. 568-574. (Full version is available as UCLA Tech. Report 95-00031.)

  50. Kleinrock, L., M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, J. Bannister, S. Monacos, T. Bujewski, P. C. Hu, B. Kannan, B. Kwan, E. Leonardi, J. Peck, P. Palnati, and S. Walton, "The Supercomputer Supernet(SSN): A High-Speed Electro-Optic Campus and Metropolitan Network". Proc. SPIE, San Jose, CA, Jan. 1996, Vol. 2692, pp. 22-33.

  51. Cong, J., J. Peck, and Y. Ding, "RASP: A General Logic Synthesis System for SRAM-based FPGAs", Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, Feb. 1996.

  52. Okamoto. T. and J. Cong, "Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion", Proc. 5th ACM/SIGDA Physical Design Workshop", Reston Virginia, April 1996, pp. 1-6.

  53. Cong, J. and L. He "Simultaneous Transistor and Interconnect Sizing Using General Dominance", Proc. 5th ACM/SIGDA Physical Design Workshop, Reston Virginia, April 1996, pp. 34-39.

  54. Cong, J. and Y. Y. Hwang "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design", Proc. 33rd ACM/IEEE Design Automation Conf., June 1996, pp. 726-729.

  55. Cong, J. , C. K. Koh, and K. S. Leung, "Simultaneous Buffer and Wire Sizing for Performance and Power Optimization", Proc. IEEE Int'l Symp. on Low Power Electronics and Design., Monterey, CA., Aug. 1996, pp 271-276.

  56. Cong, J. and C. Wu "An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design", Proc. IEEE Int'l Conf. on Computer Design, Austin, Texas, Oct. 1996, pp. 572-578.

  57. Okamoto, T. and J. Cong, "Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization, Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA., Nov. 1996, pp. 44-49.

  58. Cong, J. and L. He "An Efficient Approach to Simultaneous Transistor and Interconnect Sizing", Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA., Nov. 1996, pp. 181-186.

  59. Cong, J. "VLSI Devices and Interconnects In Deep Submicron Design", Proc. Asia and South Pacific Design Automation Conf., Chiba, Japan, Jan. 1997, pp. 121-126.

  60. Cong, J. and Y. Hwang "Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping" Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, CA., Feb. 1997, pp. 35-42.

  61. Cong, J. and Patrick H. Madden "Performance Driven Global Routing for Standard Cell Design" Proc. Intl Symposium on Physical Design, Napa, CA, April 1997, pp 73-80.

  62. Cong, J., A. B. Kahng and Kwok-Shing Leung "Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design" Proc. Intl Symposium on Physical Design, Napa, CA, April 1997, pp. 88-95.

  63. Cong, J. and Kwok-Shing Leung "Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem" Proc. Intl Symposium on Circuits and Systems, May 1997, pp. 1568-1571.

  64. Chang, C.-C. and J. Cong "An Efficient Approach to Multi-layer Layer Assignment with Application to Via Minimization", Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, CA., June 1997, pp. 600-603

  65. Cong, J., L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen "Analysis and Justification of a Simple, Practical 2 2/1-D Capacitance Extraction Methodology" Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, CA., June 1997, pp. 627-632

  66. Cong, J. and C. Wu "FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits" Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, CA., June 1997, pp. 644-649

  67. Cong, J., H. P. Li, S. K. Lim, T. Shibuya and D. Xu "Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering" Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA., Nov. 1997, pp. 441-446

  68. Cong, J., L. He, K. Y. Khoo, C. K. Koh and Z. Pan "Interconnect Design for Deep Submicron ICs" Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA., Nov. 1997, pp. 478-485. (Invited Embedded Tutorial)

  69. Cong, J., L. He, C. K. Koh and Z. Pan "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance" Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA., Nov. 1997, pp. 628-633

  70. Cong, J., and C. K. Koh "Interconnect Layout Optimization Under Higher-Order RLC Model" Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA., Nov. 1997, pp. 713-720

  71. Cong, J. and Y. Hwang "Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 27-34

  72. Cong, J. and S. Xu "Technology Mapping for FPGAs with Embedded Memory Blocks" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 179-188

  73. Cong, J. and L. He "An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs" ACM Int'l Symposium on Physical Design , pp 45-51, April, 1998

  74. Cong, J. and C. Wu "Optimal FPGA Mapping and Retiming with Efficient Initial State Computation" Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 330-335

  75. Cong, J. and P. Madden "Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs" Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 356-361

  76. Cong, J. and Z. Pan "Interconnect Performance Estimation Models for Synthesis and Design Planning" ACM/IEEE Int'l Workshop on Logic Synthesis, June, 1998, pp. 427-433

  77. Cong, J. and S. Xu "Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs" Proc. of 35th Design Automation Conf., San Francisco, CA., Jun. 1998, pp. 704-707

  78. Cong, J. and S. Xu "Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources" Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1998, pp. 40-45.

  79. Kirovski, D., Y.-Y. Hwang, M. Potkonjak, and J. Cong "Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions" Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1998, pp. 194-198

  80. J. Cong and S. K. Lim "Multiway Partitioning with Pairwise Movement" Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1998, pp. 512-516

  81. Cong, J., T. Kong, D. Xu, F. Liang, J. S. Liu and W. H. Wong "Relaxed Simulated Tempering for VLSI Floorplan Designs" Proc. of ASP-DAC'99 Hong Kong, China, Jan. 1999, pp. 13-16

  82. Cong, J. and D. Z. Pan "Interconnect Delay Estimation Models for Synthesis and Design Planning" Proc. of ASP-DAC'99 Hong Kong, China, Jan. 1999, pp. 97-100.

  83. Cong, J., C. Wu and E. Ding, "Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution" Proc. ACM Intl. Symp. on FPGA, Monterey, CA, Feb. 1999, pp. 29-35.

  84. Chang, C.-C. and J. Cong "Crosstalk Noise Control in Gridless General-Area Routing", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey, CA, pp. 117-122

  85. Cong, J. and David Z. Pan "Interconnect Delay and Area Estimation for Multiple-Pin Nets", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey, CA, pp. 179-184

  86. Cong, J., J. Fang and K.-Y. Khoo "Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms" Proc. Intl Symposium on Physical Design, Monterey, CA, April 1999, pp. 214-220

  87. Jason Cong "An Interconnect-Centric Design Flow for Nanometer Technologies", Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 1999, pp. 54-57. (Invited Talk)

  88. Jason Cong, Yean-Yow Hwang, and Songjie Xu, "Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections", Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, LA., June, 1999, pp. 373-378

  89. Jason Cong, H. Li and C. Wu "Simutanious Circuit Partitioning/Clustering with Retiming for Performance Optimization", Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, LA., June, 1999, pp. 460-465

  90. Jason Cong and D.Z. Pan "Interconnect Estimation and Planning for Deep Submicron Designs" Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, LA., June, 1999, pp. 507-510

  91. Jason Cong, J. Fang and K.Y. Khoo "An Implicit Connection Graph Maze Routing Algorithm for ECO Routing", Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1999, pp. 163-167

  92. Jason Cong, T. Kong and D.Z. Pan "Buffer Block Planning for Interconnect-Driven Floorplanning", Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, CA., Nov., 1999, pp. 358-363

  93. Jason Cong and Songjie Xu, "Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs", Asia and South Pacific Design Automation Conference, Yokohama, Japan, Jan. 2000, pp. 157-162. (Invited Talk)

  94. J. Cong and S. K. Lim "Edge Separability based Circuit Clustering With Application to Circuit Partitioning", Asia South Pacific Design Automation Conference, Yokohama Japan, Jan. 2000, pp. 429-434

  95. J. Cong and S. K. Lim "Performance Driven Multiway Partitioning", Asia South Pacific Design Automation Conference, Yokohama Japan, Jan. 2000, pp. 441-446

  96. M. Wang, S. K. Lim, J. Cong, and M. Sarrafzadeh "Multi-way Partitioning Using Bi-partition Heuristics", Asia South Pacific Design Automation Conference, Yokohama Japan, Jan. 2000, pp. 667-672

  97. Jason Cong, H. Huang and X. Yuan, "Technology Mapping for k/m-macrocell Based FPGAs", Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, CA., Feb. 2000, pp. 51-59

  98. Jason Cong and K. Yan, "Synthesis for FPGAs with Embedded Memory Blocks", Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, CA., Feb. 2000, pp. 75-82

  99. Jason Cong and Majid Sarrafzadeh, "Incremental Physical Design", Proc. International Symposium on Physical Design, , San Diego, CA., April 2000, pp. 84-92

  100. Chin-Chih Chang and Jason Cong, "Pseudo Pin Assignment with Crosstalk Noise Control", Proc. International Symposium on Physical Design, , San Diego, CA., April 2000, pp. 41-47

  101. Jason Cong, Jie Fang and Kei-Yong Khoo, "DUNE: A Multi-Layer Gridless Routing System with Wire Planning", Proc. International Symposium on Physical Design, , San Diego, CA., April 2000, pp. 12-18

  102. Jason Cong and X. Yuan, "Routing Tree Construction Under Fixed Buffer Locations", Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, CA., June 2000, pp. 379-384

  103. Jason Cong and Hui Huang, "Depth Optimal Incremental Mapping for Field Programmable Gate Arrays", Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, CA., June 2000, pp. 290-293

  104. Jason Cong, Sung Kyu Lim, and Chang Wu, "Performance Driven Multi-level and Multiway Partitioning With Retiming", Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, CA., June 2000, pp. 274-279

  105. Jason Cong, Hui Huang, Yean-Yow Hwang, Chang Wu and Songjie Xu, "fpgaEva: A Logic-Level Architechture Evaluator for SRAM-Based FPGAs", Proc. of 16th IFIP World Computer Congress - ICDA'2000: Chip Design Automation, Beijing, P.R. China, Aug 2000, pp. 179-184

  106. Jason Cong and Sung Kyu Lim, "Physical Planning with Retiming", Proc. IEEE International Conference on Computer Aided Design, San Jose, CA., Nov 2000, pp. 2-7

  107. Tony Chan, Jason Cong, Tianming Kong and Joseph Shinnerl, "Multilevel Optimization for Large-scale Circuit Placement", Proc. IEEE International Conference on Computer Aided Design, San Jose, CA., Nov 2000, pp. 171-176

  108. Olivier Goundert, Jason Cong, Sharad Malik and Majid Sarrafzadeh, "Incremental CAD", Proc. IEEE International Conference on Computer Aided Design, San Jose, CA., Nov 2000, pp. 236-243

  109. D. Chen, J. Cong, M. Ercegovac and Z. Huang, "Performance-Driven Mapping for CPLD Architecture", Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb 2001, pp. 39-47

  110. G. Chen and J. Cong, "Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs", Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb 2001, pp. 48-55