ÿþ<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv=Content-Type content="text/html; charset=unicode"> <meta name=ProgId content=Word.Document> <meta name=Generator content="Microsoft Word 12"> <meta name=Originator content="Microsoft Word 12"> <link rel=File-List href="press_files/filelist.xml"> <link rel=Edit-Time-Data href="press_files/editdata.mso"> <!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--> <title>Prof. Cong in the News</title> <!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>Janice Martin-Wheeler</o:Author> <o:Template>Normal</o:Template> <o:LastAuthor>Kirill Minkovich</o:LastAuthor> <o:Revision>13</o:Revision> <o:TotalTime>122</o:TotalTime> <o:Created>2004-09-30T21:47:00Z</o:Created> <o:LastSaved>2008-04-18T21:14:00Z</o:LastSaved> <o:Pages>3</o:Pages> <o:Words>1320</o:Words> <o:Characters>10568</o:Characters> <o:Company>UCLA Computer Science</o:Company> <o:Lines>88</o:Lines> <o:Paragraphs>23</o:Paragraphs> <o:CharactersWithSpaces>11865</o:CharactersWithSpaces> <o:Version>12.00</o:Version> </o:DocumentProperties> </xml><![endif]--> <link rel=themeData href="press_files/themedata.thmx"> <link rel=colorSchemeMapping href="press_files/colorschememapping.xml"> <!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>140</w:Zoom> <w:SpellingState>Clean</w:SpellingState> <w:GrammarState>Clean</w:GrammarState> <w:TrackMoves/> <w:TrackFormatting/> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:DoNotPromoteQF/> <w:LidThemeOther>EN-US</w:LidThemeOther> <w:LidThemeAsian>X-NONE</w:LidThemeAsian> <w:LidThemeComplexScript>X-NONE</w:LidThemeComplexScript> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> <w:DontGrowAutofit/> <w:SplitPgBreakAndParaMark/> <w:DontVertAlignCellWithSp/> <w:DontBreakConstrainedForcedTables/> <w:DontVertAlignInTxbx/> <w:Word11KerningPairs/> <w:CachedColBalance/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> <m:mathPr> <m:mathFont m:val="Cambria Math"/> <m:brkBin m:val="before"/> <m:brkBinSub m:val="&#45;-"/> <m:smallFrac m:val="off"/> <m:dispDef/> <m:lMargin m:val="0"/> <m:rMargin m:val="0"/> <m:defJc m:val="centerGroup"/> <m:wrapIndent m:val="1440"/> <m:intLim m:val="subSup"/> <m:naryLim m:val="undOvr"/> </m:mathPr></w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" DefUnhideWhenUsed="true" DefSemiHidden="true" DefQFormat="false" DefPriority="99" LatentStyleCount="267"> <w:LsdException Locked="false" Priority="0" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Normal"/> <w:LsdException Locked="false" Priority="9" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="heading 1"/> <w:LsdException Locked="false" Priority="9" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="heading 2"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 3"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 4"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 5"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 6"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 7"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 8"/> <w:LsdException Locked="false" Priority="9" QFormat="true" Name="heading 9"/> <w:LsdException Locked="false" Priority="39" Name="toc 1"/> <w:LsdException Locked="false" Priority="39" Name="toc 2"/> <w:LsdException Locked="false" Priority="39" Name="toc 3"/> <w:LsdException Locked="false" Priority="39" Name="toc 4"/> <w:LsdException Locked="false" Priority="39" Name="toc 5"/> <w:LsdException Locked="false" Priority="39" Name="toc 6"/> <w:LsdException Locked="false" Priority="39" Name="toc 7"/> <w:LsdException Locked="false" Priority="39" Name="toc 8"/> <w:LsdException Locked="false" Priority="39" Name="toc 9"/> <w:LsdException Locked="false" Priority="35" QFormat="true" Name="caption"/> <w:LsdException Locked="false" Priority="10" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Title"/> <w:LsdException Locked="false" Priority="1" Name="Default Paragraph Font"/> <w:LsdException Locked="false" Priority="11" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtitle"/> <w:LsdException Locked="false" Priority="22" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Strong"/> <w:LsdException Locked="false" Priority="20" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Emphasis"/> <w:LsdException Locked="false" Priority="59" SemiHidden="false" UnhideWhenUsed="false" Name="Table Grid"/> <w:LsdException Locked="false" UnhideWhenUsed="false" Name="Placeholder Text"/> <w:LsdException Locked="false" Priority="1" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="No Spacing"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 1"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 1"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 1"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 1"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 1"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 1"/> <w:LsdException Locked="false" UnhideWhenUsed="false" Name="Revision"/> <w:LsdException Locked="false" Priority="34" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="List Paragraph"/> <w:LsdException Locked="false" Priority="29" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Quote"/> <w:LsdException Locked="false" Priority="30" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Intense Quote"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 1"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 1"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 1"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 1"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 1"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 1"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 1"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 1"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 2"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 2"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 2"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 2"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 2"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 2"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 2"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 2"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 2"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 2"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 2"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 2"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 2"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 2"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 3"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 3"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 3"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 3"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 3"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 3"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 3"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 3"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 3"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 3"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 3"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 3"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 3"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 3"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 4"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 4"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 4"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 4"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 4"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 4"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 4"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 4"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 4"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 4"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 4"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 4"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 4"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 4"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 5"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 5"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 5"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 5"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 5"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 5"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 5"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 5"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 5"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 5"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 5"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 5"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 5"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 5"/> <w:LsdException Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 6"/> <w:LsdException Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 6"/> <w:LsdException Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 6"/> <w:LsdException Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 6"/> <w:LsdException Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 6"/> <w:LsdException Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 6"/> <w:LsdException Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 6"/> <w:LsdException Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 6"/> <w:LsdException Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 6"/> <w:LsdException Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 6"/> <w:LsdException Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 6"/> <w:LsdException Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 6"/> <w:LsdException Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 6"/> <w:LsdException Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 6"/> <w:LsdException Locked="false" Priority="19" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtle Emphasis"/> <w:LsdException Locked="false" Priority="21" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Intense Emphasis"/> <w:LsdException Locked="false" Priority="31" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtle Reference"/> <w:LsdException Locked="false" Priority="32" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Intense Reference"/> <w:LsdException Locked="false" Priority="33" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Book Title"/> <w:LsdException Locked="false" Priority="37" Name="Bibliography"/> <w:LsdException Locked="false" Priority="39" QFormat="true" Name="TOC Heading"/> </w:LatentStyles> </xml><![endif]--> <style> <!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Verdana; panose-1:2 11 6 4 3 5 4 4 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:536871559 0 0 0 415 0;} @font-face {font-family:Times; panose-1:2 2 6 3 5 4 5 2 3 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:536881799 -2147483648 8 0 511 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; mso-margin-top-alt:auto; margin-right:0in; mso-margin-bottom-alt:auto; margin-left:0in; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman"; mso-bidi-font-family:"Times New Roman";} h2 {mso-style-priority:9; mso-style-unhide:no; mso-style-qformat:yes; mso-style-link:"Heading 2 Char"; mso-margin-top-alt:auto; margin-right:0in; mso-margin-bottom-alt:auto; margin-left:0in; mso-pagination:widow-orphan; mso-outline-level:2; font-size:18.0pt; font-family:"Times New Roman","serif"; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; font-weight:bold;} a:link, span.MsoHyperlink {mso-style-priority:99; color:blue; text-decoration:underline; text-underline:single;} a:visited, span.MsoHyperlinkFollowed {mso-style-noshow:yes; mso-style-priority:99; color:blue; text-decoration:underline; text-underline:single;} p {mso-style-noshow:yes; mso-style-priority:99; mso-margin-top-alt:auto; margin-right:0in; mso-margin-bottom-alt:auto; margin-left:0in; mso-pagination:widow-orphan; font-size:12.0pt; font-family:"Times New Roman","serif"; mso-fareast-font-family:"Times New Roman";} span.Heading2Char {mso-style-name:"Heading 2 Char"; mso-style-noshow:yes; mso-style-priority:9; mso-style-unhide:no; mso-style-locked:yes; mso-style-link:"Heading 2"; mso-ansi-font-size:13.0pt; mso-bidi-font-size:13.0pt; font-family:"Cambria","serif"; mso-ascii-font-family:Cambria; mso-ascii-theme-font:major-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:major-fareast; mso-hansi-font-family:Cambria; mso-hansi-theme-font:major-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:major-bidi; color:#4F81BD; mso-themecolor:accent1; font-weight:bold;} span.SpellE {mso-style-name:""; mso-spl-e:yes;} span.GramE {mso-style-name:""; mso-gram-e:yes;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; font-size:10.0pt; mso-ansi-font-size:10.0pt; mso-bidi-font-size:10.0pt;} @page Section1 {size:8.5in 11.0in; margin:1.0in 1.25in 1.0in 1.25in; mso-header-margin:.5in; mso-footer-margin:.5in; mso-paper-source:0;} div.Section1 {page:Section1;} --> </style> <!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";} </style> <![endif]--> <meta name=Title content="JASON CONG'S HOME PAGE"> <meta name=Keywords content=""> <!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="1026"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--> </head> <body bgcolor=white lang=EN-US link=blue vlink=blue style='tab-interval:.5in'> <div class=Section1> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='mso-fareast-font-family:"Times New Roman"'>Prof. Cong in the News<o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE Times : Future of chip design revealed at ISPD (May 2008)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>Another paper of note, according to ISPD general chair David Pan, <span class=SpellE>an</span> EE Professor at the University of Texas (Austin), was one showing how to create ultra-high-speed on-chip interconnects using radio frequency (RF) transmission lines. This was presented by Professors Frank Chang and Jason Cong of the University of California at Los Angeles (UCLA). In this interconnect scheme, data is transmitted by modulating an electromagnetic wave along an RF transmission line that can be implemented using standard CMOS processing steps.</span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <p class=MsoNormal style='margin:0in;margin-bottom:.0001pt;line-height:17.0pt; mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt;mso-bidi-font-family:Times;mso-bidi-font-weight:bold'><a href="http://www.eetimes.com/news/design/showArticle.jhtml?articleID=207400313">http://www.eetimes.com/news/design/showArticle.jhtml?articleID=207400313</a><o:p></o:p></span></p> <p class=MsoNormal style='margin:0in;margin-bottom:.0001pt;line-height:17.0pt; mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt;mso-bidi-font-family:Times;mso-bidi-font-weight:bold'><o:p>&nbsp;</o:p></span></p> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span class=SpellE><span class=GramE><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family: "Times New Roman"'>SCDsource</span></span></span><span class=GramE><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'> :</span></span><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt; mso-fareast-font-family:"Times New Roman"'> Multi-band RF interconnect speeds network-on-chip (Jan 2008)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>Researchers at the University of California at Los Angeles (UCLA) have developed a multi-band RF interconnect technology that boosts communications speeds and reduces latency in <span class=SpellE>multicore</span> ICs. The technology will &quot;open a new wave in on-chip communications,&quot; says Jason Cong, chairman of UCLA's computer science department.</span><span style='font-size: 14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif";mso-fareast-font-family: "Times New Roman"'><o:p></o:p></span></h2> <p class=MsoNormal style='margin:0in;margin-bottom:.0001pt;line-height:17.0pt; mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt;mso-bidi-font-family:Times;mso-bidi-font-weight:bold'><a href="http://www.scdsource.com/article.php?id=77">http://www.scdsource.com/article.php?id=77</a> <o:p></o:p></span></p> <p class=MsoNormal style='margin:0in;margin-bottom:.0001pt;line-height:17.0pt; mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt;mso-bidi-font-family:Times;mso-bidi-font-weight:bold'><o:p>&nbsp;</o:p></span></p> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>UCLA <span class=GramE>Newsroom :</span> UCLA scientists working to create smaller, faster integrated circuits (Dec 2007)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>Integrated circuits are the &quot;brain&quot; in computers, cell phones, DVD players, <span class=SpellE>iPhones</span>, personal digital assistants, automobiles' navigation systems and anti-lock brakes, and many other electronic devices. A team of UCLA scientists has now demonstrated substantial improvements in integrated circuits, achieved not by costly improvements in manufacturing but by improved computer-aided design software based on better mathematical algorithms.</span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt; font-family:"Times","serif";mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal;mso-bidi-font-weight: bold'><a href="http://www.newsroom.ucla.edu/portal/ucla/ucla-scientists-make-major-advance-41151.aspx">http://www.newsroom.ucla.edu/portal/ucla/ucla-scientists-make-major-advance-41151.aspx</a><o:p></o:p></span></h2> <h2 align=center style='text-align:center;line-height:17.0pt;mso-line-height-rule: exactly'> <hr size=2 width="100%" align=center> </h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span class=SpellE><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>SolidState</span></span><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'> <span class=GramE>Technology :</span> Moore's Law to head z-ward? (Nov 2007)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>While the industry struggles to continue on the Moore's Law track, 3D approaches superior to those of systems-on-chip may provide an interim solution if the shrink slows down. A SEMATECH-organized workshop in Albany, NY earlier this month (Oct. 11-12) addressed fundamental issues about 3D, including four reasons why every chipmaker has 3D/TSV approaches on its roadmap, and what needs to be solved before 3D can be effective beyond simple memory.</span><span style='mso-fareast-font-family:"Times New Roman"'> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://sst.pennnet.com/display_article/310451/5/ARTCL/none/none/1/Moore's-Law-to-head-z-ward?/">http://sst.pennnet.com/display_article/310451/5/ARTCL/none/none/1/Moore's-Law-to-head-z-ward?/</a><span style='mso-spacerun:yes'>   </span><o:p></o:p></span></h2> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE <span class=GramE>TIMES :</span> Plain-vanilla EDA gets its due (Sep 2006)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>These days, the excitement in EDA centers on electronic system-level tools and design-for-manufacturability. But unsolved problems remain in plain-vanilla synthesis, placement and routing.</span><span style='mso-fareast-font-family: "Times New Roman"'> </span><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt;font-family:"Times","serif";mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.eetimes.com/showArticle.jhtml?articleID=188500070">http://www.eetimes.com/showArticle.jhtml?articleID=188500070</a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE TIMES : Optimization techniques rein in IC POWER FLOW (May 2006)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>In the effort to save power consumption, chip designers increasingly are turning to such techniques as power gating--which requires behavioral simulation and intelligent placement of power-gating transistors--as well as voltage reduction, frequency scaling and limiting accesses to off-chip memory.</span><span style='mso-fareast-font-family:"Times New Roman"'> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.eetimes.com/news/design/showArticle.jhtml?articleID=187201880">http://www.eetimes.com/news/design/showArticle.jhtml?articleID=187201880</a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>FPGA JOURNAL : Blaming the Button -- Physical Synthesis Moves to Mainstream (April 2006)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>According to a recent paper published by Jason Cong and Kirill Minkovich of UCLA, the optimality of logic design alone can be off by as much as 70-500X. That's not a percent sign, boys and girls; that big X means that your design may be taking up 70 to 500 times as many LUTs as the best possible solution. The UCLA study compared synthesis results from academic and commercial synthesis tools with known-optimal solutions for a variety of circuits. The paper says that the synthesis tools were 70 times larger in area on average than the known optimal solutions in the test study. </span><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt;font-family:"Times","serif";mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.fpgajournal.com/articles_2006/20060425_button.htm">http://www.fpgajournal.com/articles_2006/20060425_button.htm</a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'>EE TIMES :</span></b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'> </span><b><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt'>Huge FPGA synthesis gap seen -- Circuits may be 70x larger than optimal </span></b><b><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>(February 2006)</span></b><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'><br> Anyone who thinks FPGA synthesis is a solved problem will get a rude awakening at the FPGA 2006 conference here this week. That's when an eminent CAD researcher will show that current synthesis tools may produce circuits that are 70 to 500 times larger than the known optimal solutions in synthetic benchmarks. <o:p></o:p></span></p> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><a href="http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=180204087"><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=180204087</span></a><b><o:p></o:p></b></p> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>World Journal Daily About Prof. <span class=SpellE>Cong's</span> Talk in PUAASC 2005 Annual <span class=GramE>Convention :</span> Design Our Career, or Can We? -- Reflection from an Engineering Professor </span><span style='font-size:14.0pt; mso-bidi-font-size:10.0pt;font-family:"Times","serif";mso-fareast-font-family: "Times New Roman"'><o:p></o:p></span></h2> <p class=MsoNormal style='margin:0in;margin-bottom:.0001pt;line-height:17.0pt; mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size: 18.0pt;font-family:"Times New Roman","serif"'><a href="http://www.worldjournal.com/wj-la-news.php?nt_seq_id=1237232">http://www.worldjournal.com/wj-la-news.php?nt_seq_id=1237232</a><o:p></o:p></span></p> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:12.0pt;font-family:"Times New Roman","serif"'> <hr size=2 width="100%" align=center> </span></div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>FPGA <span class=GramE>JOURNAL :</span> Power -- Suddenly, We Care (April 2005)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>For years it was like a slogan. &quot;FPGAs are nice, but they're power hogs.&quot; If a new FPGA family offered a 50% performance increase or doubled the LUT count over the previous generation, damn the <span class=SpellE>heatsinks</span> and full-speed ahead. Designers rolled FPGAs in with reckless abandon. Today, however, forces are conspiring to bring power concerns off of the back burner and into the forefront of FPGA design consideration. </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.fpgajournal.com/articles_2005/20050426_power.htm">http://www.fpgajournal.com/articles_2005/20050426_power.htm</a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'>EE <span class=GramE>TIMES :</span></span></b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'> </span><b><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt'>IC floor planning moves ahead </span></b><b><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>(January 2005)</span></b><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'><br> A new approach to IC floor-planning developed by UCLA researchers is said to reduce wire length while running orders of magnitude faster than previous solutions. The approach was disclosed at the recent ASP-DAC conference in Shanghai.<o:p></o:p></span></p> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><a href="http://www.eetimes.com/showArticle.jhtml?articleID=59100114"><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>http://www.eetimes.com/showArticle.jhtml?articleID=59100114</span></a><b><o:p></o:p></b></p> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>FPGA <span class=GramE>JOURNAL :</span> Training Tomorrow's Talent (August 2004)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family: "Times","serif";mso-fareast-font-family:"Times New Roman";font-weight:normal'>Professor Jason Cong is profiled in the latest issue of FPGA and Programmable Logic Journal. Cong, who is described as a &quot;modern-day luminary&quot; and &quot;master educator,&quot; has trained some of the best technical talent in the FPGA design tools industry today.</span><span style='font-size:14.0pt; mso-bidi-font-size:10.0pt;font-family:"Times","serif";mso-fareast-font-family: "Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;font-family:"Times","serif"; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.fpgajournal.com/articles/20040831_cong.htm">http://www.fpgajournal.com/articles/20040831_cong.htm</a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE TIMES : Power, crosstalk crisis to reroute IC design flows (April 2004)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;mso-fareast-font-family: "Times New Roman";font-weight:normal'>Power and signal-integrity problems are approaching critical mass and will soon force changes in the nanometer IC design flow. But CAD methodology experts speaking at the Electronic Design Processes 2004 workshop said that the industry is on the case. </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;mso-fareast-font-family:"Times New Roman"'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;mso-fareast-font-family:"Times New Roman"; font-weight:normal'><a href="http://www.eetimes.com/article/showArticle.jhtml?articleId=19400044&amp;sub_taxonomyID=4217">http://www.eetimes.com/article/showArticle.jhtml?articleId=19400044&amp;sub_taxonomyID=4217</a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'>EE <span class=GramE>TIMES :</span></span></b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'> </span><b><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt'>FPGA placement performs poorly, study says</span></b><b><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt'> (November 2003)</span></b><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt'><br> Timing-driven placement algorithms for FPGAs can be as much as 50 percent away from optimal results, according to a paper given at the 2003 International Conference on Computer-Aided Design (ICCAD). <o:p></o:p></span></p> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><a href="http://www.eedesign.com/story/OEG20031113S0048"><span style='font-size: 14.0pt;mso-bidi-font-size:10.0pt'>http://www.eedesign.com/story/OEG20031113S0048</span></a><b><o:p></o:p></b></p> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE TIMES : </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt; mso-fareast-font-family:"Times New Roman"'>Magma acquisition targets structured ASIC market (June 2003)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family: "Times New Roman";font-weight:normal'>Making a bold entry into a marketplace barely touched by the big EDA vendors, Magma Design Automation confirmed that it has purchased Los Angeles-based PLD synthesis company <span class=SpellE>Aplus</span> Design Technologies to enter the emerging structured ASIC market.<o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span class=MsoHyperlink><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.eedesign.com/showArticle.jhtml?articleID=17408431">http://www.eedesign.com/showArticle.jhtml?articleID=17408431</a></span><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE TIMES : </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt; mso-fareast-font-family:"Times New Roman"'>IC placement benchmarks needed, researchers say (April 2003) <br> </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family: "Times New Roman";font-weight:normal'>Following up on a controversial study that claimed IC placement algorithms are severely deficient, researchers at the International Symposium on Physical Design (ISPD) struggled to find a benchmarking methodology for IC physical design.<o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span class=MsoHyperlink><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.eedesign.com/showArticle.jhtml?articleID=17408299">http://www.eedesign.com/showArticle.jhtml?articleID=17408299</a></span><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE <span class=GramE>TIMES :</span> </span><span style='font-size:14.0pt; mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman"'>ISPD to present call for EDA benchmarking (April 2003)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family: "Times New Roman";font-weight:normal'>A call for open benchmarking of IC placement tools will be among the topics at the 2003 International Symposium on Physical Design (ISPD). ISPD will also review the latest research in topics such as physical synthesis, timing, partitioning, power grid design, lithography, routing, and circuit fabrics.<o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span class=MsoHyperlink><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt; mso-fareast-font-family:"Times New Roman";font-weight:normal'><a href="http://www.eedesign.com/showArticle.jhtml?articleID=17408310">http://www.eedesign.com/showArticle.jhtml?articleID=17408310</a></span><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE TIMES : </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt; mso-fareast-font-family:"Times New Roman"'>Placement tools criticized for hampering IC designs (February 2003)<br> </span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family: "Times New Roman";font-weight:normal'>Current IC placement algorithms leave so much excess wire that chip designs are essentially several technology generations behind where they could be, according to a recent paper by researchers at the University of California at Los Angeles (UCLA).</span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman"'> <o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman"'><a href="http://www.eedesign.com/showArticle.jhtml?articleID=17408185"><span style='mso-bidi-font-size:10.0pt;font-weight:normal'>http://www.eedesign.com/showArticle.jhtml?articleID=17408185</span></a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'>EE <span class=GramE>TIMES :</span></span></b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'> </span><b><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt'>FPGA synthesis tools lose battle with John Henry</span></b><b><span style='font-size:14.0pt;mso-bidi-font-size: 10.0pt'> (February 2000)</span></b><span style='font-size:14.0pt;mso-bidi-font-size: 7.5pt'> <b><br> </b></span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>In American folklore, John Henry represents man's struggle against obsolescence. Legend has it that John Henry and his sledgehammer beat a steam-powered drill in a tunnel-digging contest, but his heart burst in the effort. An evening panel at FPGA 2000 entitled &quot;The John Henry Syndrome&quot; recast that legend in the FPGA world, asking whether software tools can ever outpace human intervention. </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt; font-family:"Verdana","sans-serif"'><o:p></o:p></span></p> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><a href="http://www.eetimes.com/article/showArticle.jhtml?articleId=18303632&amp;sub_taxonomyID="><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>http://www.eetimes.com/article/showArticle.jhtml?articleId=18303632</span></a><span style='mso-bidi-font-size:7.5pt'><o:p></o:p></span></p> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt;mso-fareast-font-family:"Times New Roman"'>EE <span class=GramE>TIMES :</span> </span><span style='font-size:14.0pt; mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman"'>Startup rethinks FPGA synthesis (February 2000)</span><span style='font-size:14.0pt; mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman";font-weight: normal'><br> An EDA startup with close ties to the University of California at Los Angeles (UCLA) is quietly preparing next-generation synthesis for large, high-performance PLDs. The startup, <span class=SpellE>Aplus</span> Design Technologies (ADT), came to light at the FPGA 2000 Conference in Monterey with the announcement of a partnership with Cypress Semiconductor Inc.<o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman"; font-weight:normal'><a href="http://www.eedesign.com/showArticle.jhtml?articleID=17405549"><span style='mso-bidi-font-size:10.0pt'>http://www.eedesign.com/showArticle.jhtml?articleID=17405549</span></a><o:p></o:p></span></h2> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'>EE <span class=GramE>TIMES :</span></span></b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'> </span><b><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt'>Panel debates synthesis-layout integration</span></b><b><span style='font-size:14.0pt; mso-bidi-font-size:10.0pt'> (April 1999)</span></b><span style='font-size:14.0pt; mso-bidi-font-size:7.5pt'> <b><br> </b></span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>The difficult issue of whether, and how, to integrate logical and physical design surfaced anew at the International Symposium on Physical Design (ISPD-99), where EDA vendors and academic professors joined a sometimes contentious panel on &quot;layout-driven synthesis or synthesis-driven layout.&quot; <o:p></o:p></span></p> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><a href="http://www.eetimes.com/article/showArticle.jhtml?articleId=18301566&amp;sub_taxonomyID=4217"><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>http://www.eetimes.com/article/showArticle.jhtml?articleId=18301566&amp;sub_taxonomyID=4217</span></a><b><span style='mso-bidi-font-size:7.5pt'><o:p></o:p></span></b></p> <div style='margin-top:5.0pt;margin-bottom:5.0pt'> <div class=MsoNormal align=center style='margin:0in;margin-bottom:.0001pt; text-align:center;line-height:17.0pt;mso-line-height-rule:exactly'> <hr size=2 width="100%" align=center> </div> </div> <p style='line-height:17.0pt;mso-line-height-rule:exactly'><b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'>EE TIMES :</span></b><span style='font-size:14.0pt;mso-bidi-font-size:12.0pt'> </span><b><span style='font-size:14.0pt;mso-bidi-font-size:18.0pt'>ICCAD probes tools for billion-transistor designs</span></b><span style='font-size:14.0pt;mso-bidi-font-size: 12.0pt'> <b>(November 1998)</b><br> </span><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt'>Architectural and physical design must be brought closer together to handle billion-transistor designs, according to panelists at this week's International Conference on Computer-Aided Design (ICCAD 98). The Semiconductor Industry Association's National Technology Roadmap predicts billion-transistor chips by 2010.</span><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></p> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='font-size:14.0pt;mso-bidi-font-size:10.0pt;mso-fareast-font-family:"Times New Roman"; font-weight:normal'><a href="http://www.eetimes.com/article/showArticle.jhtml?articleId=18300460&amp;sub_taxonomyID=">http://www.eetimes.com/article/showArticle.jhtml?articleId=18300460</a></span><span style='font-size:14.0pt;mso-bidi-font-size:7.5pt;mso-fareast-font-family:"Times New Roman"; font-weight:normal'><o:p></o:p></span></h2> <h2 style='line-height:17.0pt;mso-line-height-rule:exactly'><span style='mso-fareast-font-family:"Times New Roman"'><o:p>&nbsp;</o:p></span></h2> <p class=MsoNormal style='margin:0in;margin-bottom:.0001pt;line-height:17.0pt; mso-line-height-rule:exactly'><span style='mso-bidi-font-family:Times'><o:p>&nbsp;</o:p></span></p> </div> </body> </html>