Invited Talks and Tutorials

• Frank Chang, Jason Cong, and Glenn Reinman (UCLA), "RF-Interconnect and its Applications to NOC Design,"3rd ACM/IEEE International Symposium on Network-on-Chip (NOCS), San Diego, CA, May 2009 (NOCS Tutorial Course)

• "Thermal-Aware 3D IC Physical Design and Architecture Exploration," International 3D-System Integration Conference 2008 (3D-SIC2008), May 12-13, 2008, Tokyo, Japan (Invited Talk)

• Alberto Sangiovanni Vincentelli (UCB), Douglas Densmore (UCB), Jason Cong (UCLA), Radu Marculescu (CMU), "System-Level Synthesis - Functions, Architectures, and Communications," ASPDAC 2008, January 21-24, 2008, Seoul, Korea (Invited Talk)

• "Compilation for Domain-Specific Computing," Department of Electrical and Computer Engineering, University of Texas at Austin, September 11, 2007 (Distinguished Speaker)

• "Compilation of Domain-Specific Computing," CANDE 2007 September 6-8, 2007, Long Beach, CA. (Invited Talk)

• "Challenges and Opportunities for System/High-Level CAD and Architectures in FPGAs," Workshop on Grand Challenges in FPGA Research (in junction with International Symposium on FPGAs), February 2007. (Invited Talk)

• "Advanced Routing Techniques for Nanometer IC Designs," Routing Tutorial with Tong Gao (Synopsys, Inc.) and Rob A. Rutenbar (Carnegie Mellon Univ.) at the 2006 International Conference on Computer-Aided Design, San Jose, California, November 9, 2006.

• "3D - IC Keynote Panel Participant," VLSI Multilevel Interconnection Conference, September 2006.

• "Platform Based Behavioral and System Synthesis," 2006 IEEE Electronic Design Process Workshop, April 2006. (Invited Talk)

• "Platform Based Behavior-Level and System-Level Synthesis," Distinguished Speaker Seminar Series, Electrical and Computer Engineering, Univ. of Arizona (March 2006)

• "xPilot: A Platform-Based System-Level Synthesis for Reconfigurable SOCs," International Symposium on Advanced Reconfigurable Systems, Kyoto, Japan, Canada, December 15-16, 2005.

• "Platform-Based Synthesis for Field Programmable SOCs," IEEE 2005 Conference on Field Programmable Technology (FPT’05), Singapore, December 11-14, 2005.

• "Large-Scale Circuit Placement: Gap and Progress," University of Toronto Distinguished Lecture Series, University of Toronto, Ontario, Canada, March 24, 2005.

• "Challenges and Solutions for Nanometer SOC Designs," Invited Talk at the 2004 International SoC Design Conference, Seoul, Korea, October, 2004.

• "Architecture and Synthesis for Power-Efficient FPGA's," (Invited Dinner Speech), 2004 IEEE Electronic Design Process Symposium (EDPS), Monterey, California, April, 2004.

• "Large-Scale Circuit Placement: Gap and Promise," Embedded Tutorial presented at the 2003 International Conference on Computer-Aided Design, San Jose, California, November 12, 2003.

• "Architecture and Synthesis for Multi-Cycle On-Chip Communication,"Invited Talk at the 2003 International Conference on Hardware/Software Codesign and System Synthesis Newport Beach, California October 1, 2003.

• "Architecture and Synthesis for Multi-Cycle On-Chip Communication," Keynote Speaker, International Rapid System Prototyping Workshop, San Diego, California, June 9, 2003.

• "Large-Scale Circuit Placement: The Gap and Promise," Guest Lecturer, Georgia Institute of Technology, Atlanta, Georgia, April 17, 2003.

• "Architecture and Synthesis for Multi-Cycle Communication,"Invited Talk at the 2003 International Symposium on Physical Design, Monterrey, California, April 9, 2003.

• "Retiming/Pipelining Over Global Interconnects," The Design Automation Professional Interest Committee at IBM Research Seminal Series, Yorktown Heights, New York, June 27, 2002.

• "System Level Interconnects," FCRP Interconnect Workshop, University of Albany, June 28, 2002.

• "Timing closure Based on Physical Hierarchy," Invited talk at International Symposium on Physical Design, San Diego, Californis, April 2002.

• "An Interconnect-Centric Design Flow for Nanometer Technologies," Proceedings of the Workshop on Synthesis And Systems Integration of Mixed Technologies, Nara, Japan, October 9, 2001.

• "Physical Hierarchy Generation,"; The 3rd Intel Annual Research Symposium on Synthesis, Portland, Oregon, August 15, 2001.

• "PLD Synthesis Algorithms," a tutorial presented at the 38th Design Automation Conference, Las Vegas, June, 2001.

• "Timing Closure for Ultra Deep Submicron Designs", Asian and South Pacific Design Automation Conference, Jan 30-Feb 2, 2001.

• "An Interconnect-Centric Design Flow for Nanometer Technologies", Invited talk at Motorola's Futures Forum on Circuits, Systems, and Architectures, October 16, 2000.

• "The Quest for Synthesis and Layout Timing Closure" (full day tutorial, with Olivier Coudert, Anthony Drumm, and Patrick Groeneveld), the 37th Design Automation Conference, Los Angeles, June 9, 2000.

• "Incremental Physical Design" (Invited Talk with Majid Sarrafzadeh), Int'l Symposium on Physical Design, San Diego, CA., April 2000.

• "Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs" (Invited Talk), Asia and South Pacific Design Automation Conference Yokohama, Japan, Jan. 2000.

• "An Interconnect-Centric Design Flow for Nanometer Technologies" (Invited Talk), Int'l Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 1999.

• "FPGA Synthesis: Past, Present, and Future" (Keynote Speech), The Sixth Japanese FPGA/PLD Design Conference & Exhibit, Pacifico Yokohama, Japan, June 1998.

• "Deep Submicron Layout and Coupling to Logic Synthesis" (invited talk), International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, Dec. 16, 1997.

• "VLSI Interconnect Layout Optimization In Deep Submicron Designs", UC Berkeley CAD Seminar Series, Nov. 21, 1997.

• "Interconnect Design for Deep Submicron ICs", Embedded Tutorial, IEEE Int'l Conf. on Computer-Aided Design, Nov. 1997.

• "Interconnect-Driven Performance Optimization for Deep Submicron Layout Systems" (full day tutorial), the 34th Design Automation Conference, June 13, 1997.

• "FPGA Mapping, Retiming, and Pipelining for Performance Optimization", UC Berkeley CAD Seminar Series, Mar. 5, 1997.

• "Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design" (embedded tutorial), Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 1997.

• "Performance and Power Optimization in Synthesis and Layout of VLSI Circuits and Systems" (tutorial, with Massoud Pedram), EuroDAC'96, Geneva, Switzerland, Sept. 1996.

• "Layout Level Optimization for Low Power" (invited lecture), NATO Advanced Study Institute on Low Power Design in Deep Submicron Electronics, Tuscany, Italy, Aug. 1996.

• "Interconnect-Driven Layout for High-Performance VLSI Systems" (invited talk), Intel CAD Symposium on Frontiers of CAD, April 12, 1996.

• "Interconnect-Driven Layout Synthesis for High-Performance Low-Power VLSI Systems" (short course), Tsinghua University, Taiwan, Aug. 1995.

• "Timing-Driven Design of VLSI" (tutorial, with Raul Camposano and Michael Smith), Asia and South Pacific Design Automation Conf., Chiba, Japan, Aug. 1995.

• "Dealing with Physical Effects When Designing Deep Submicron Chips" (keynote speech), Silicon Valley Research Continuing Education Series, Austin, Texas, May 4, 1995.

• "Interconnect-Driven Layout Synthesis for High-Performance VLSI Systems" (Distinguished Faculty Speaker), Intel Corporation Design Technology Innovations Workshop, Santa Clara, California, March 1994.

• "Architecture, CAD Algorithm, and Application of SRAM-Based FPGAs" (tutorial, with Michael Butts and Stephen Trimberger) IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1993.

• "Synthesis and Optimization for FPGA Design" (tutorial, with K. C. Chen), Int'l Conf. on Computer-Aided Design and Computer Graphics, Beijing, China, Aug. 1993.

• "Performance Evaluation and Optimization in Layout Synthesis of High-Speed VLSI Systems" (tutorial, with Steve Kang and C. L. Liu), 30th ACM/IEEE Design Automation Conference, Dallas, Texas, June 1993.

• "On High-Speed VLSI Interconnects: Analysis and Design" (invited talk with Andrew B. Kahng), IEEE Asian-Pacific Conference on Circuits and Systems, Sydney, Australia, Dec. 1992.

• "Provably Good Performance-Driven Global Routing" (invited talk), Dagstuhl Seminar On Theory and Practice of VLSI Layout, Dagstuhl, Germany, Sept. 1991.

Invited Articals and Reports

• "Challenges and Opportunities for Design Innovations in Nanometer Technologies", SRC Design Sciences Concept Paper, Dec. 1997.

Back to Jason Cong's Home Page