Jeonghun Kim
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
UCLA Computer Science Department
4731A Boelter
Hall
Office)310-794-4752
Cell) 310-936-8117
Jeonghun Kim received his BS degree in
electronics engineering from
He had worked in the ISD SOC Verification Team
at Magnachip semiconductor Ltd.,
From Aug 1993 to Dec 2004, he worked as an
Optical storage system engineer at Samsung Electronics Inc., Seoul, Korea where
he did research on the optical storage servo system and system-on-chip design
and verification. His research interests are in
power-aware verification for High Level Synthesis, Multimedia and
multi-processors SOC, system-on-chip design, verification, methodology and applications
HIGHLISGHTS OF ACCOMPLISHMENTS
n
SOC Design and Verification
experience in wireless/multimedia applications
n
Successful
technical lead of team and projects, Organized, designed and planned SOC
projects
n
Successful in
developing and implementing unified verification environment and platform
-
Centralized
Data Structure consists of repository, user and common directory using CVS
(Concurrent Version System) or Subversion
-
Reusable
Verification Environment for each IP and SOC using Makefile,
perl and shell script
-
Included Whole
Design flow (Verification, synthesis, STA, SCAN, ATPG and Formality run script)
-
Project: ISP
SOC, V2.0+EDR Bluetooth SOC, COMBO 52x SOC, Transforms Processor for
Multi-Codec and Etc.
n
System level
verification with ARM, MIPI, HOST and serial interface model using SystemC, C and Verilog
n
Micro-architecture
design experience especially in ARM series and AMBA
n
Several SOC
successfully tape-out, launch and experience of whole ASIC design flow from
design specification to chip test
-
Worked on Bus
Architecture, Fullchip integration, Test scheme for
IP and peripherals
-
Developed
synthesis, SCAN, TetraMax ATPG and STA TCL scripts
-
Designed an
overall floorplan for the physical design and
collaborate with physical design engineer for timing optimization, minimized
chip size and efficient power routing.
-
Samsung, HYNIX,
SMIC, Magnachip and TSMC Fabrication experience
n
Optical Servo
Processor Development
-
Partitioned
servo controller into HW and SW, Designed Software digital Servo on DSP, SW/HW
Servo Architecture (hardwired-digital filter and automatic adjustment software
algorithm on ARM7) and Full Hardware Servo Architecture
-
Development
automatic adjust algorithm and digital filter
-
Validation and
performance test of servo
n
Familiar
with Verilog HDL, C/C++/SystemC,
TCL for synthesis, NC-Verilog, Synopsys, Formality, TetraMax, simulink, Matlab, perl, makefile
and c-shell script.
EXPERIENCE
10/2008- present, UCLA
Assistant
Researcher, Computer Science Department
n
Verification Automation with C and SystemVerilog for High Level Synthesis
n
Power-Aware verification
for High Level Synthesis
n
Low Power Design and Verification of SoC
2/2007-08/2008, Magnachip Semiconductor, Inc.
Team
Manager/Principal Research Engineer, Verification
Team, ISD (Image Solution Division)
n
Technical leading and Managing the verification
team members between
n
Handling test cases, runs and test cases
regression for fullchip/system level and leading
verification plan.
n
Coordinating roles and
tasks such as MIPI PHY model, MIPI TX RTL design and MIPI receiver model to
verify MIPI block on system/fullchip level. Collaborated
with each engineer to verify MIPI block.
Developed MIPI verification platform, test bench and test cases using these
modules for fullchip/system level
n
Working on
system/fullchip level verification with Host, ARM,
serial interface and MIPI model using SystemC and C
program
01/2005-12/2006
Mewtel
Technology, Inc.
Team Manager/
Principal Research Engineer, ASIC Team, Wireless SOC
Design Center
n
Technically
Leaded and Managed ASIC Team. Organized, designed and planned wireless
SOC projects.
n
V2.0+EDR Bluetooth
SOC Development Feb. 2005 ~ Dec. 2006,
-
This chip
consists of MCU (ARM series), Link Controller, Modem, RF
transceiver, SBC, USB, SDIO and Peripherals.
-
As system
engineer: made the chip specification. Designed bus architecture, fullchip integration, test scheme of IP blocks and
alternative path, Wrote TCL file for Synthesis, STA, SCAN and Timing Closure.
Designed overall floorplan of P&R and collaborate
with P&R engineer for timing optimization, minimized chip size and
efficient power routing. Ported USB 2.0 and SDIO which are external IP to AMBA
system and fullchip.
-
As verification
engineer: Developed and deployed unified design and verification environment
including data structure. Verified fullchip
integration and IP block on Fullchip level
-
As RTL
Engineer: Designed and verified UART, IIC, MCBSP and basic peripherals
08/1993-12/2004 Samsung Electronics Co., LTD
SOC Design and Verification Engineer/Senior MTS
Media Storage
Team, System-LSI division, Semiconductor Business
n
Optical Storage
SOC Development
Apr. 2003- Dec.2004
SOC Design
and Verification Senior Engineer/Senior Research Engineer
-
52x CDRW, COMBO
SOC with AFE (Analog Front End) ADC, DAC, PLL and Etc) and digital core (ARM,
ATAPI, CD-ENC, SERVO, CD-DEC,. Etc)
-
As SOC system
engineer: Designed full-chip integration and micro-architecture, test scheme
and mode for analog/digital IP, test bus interface replace with internal bus of
normal mode, design the overall floorplan and
collaborated with the physical design engineer for timing optimization,
minimized chip size and efficient power routing
-
As verification
engineer: setup design and verification environment using Makefile,
perl and c-shell script including from RTL design
step to post-simulation, design fullchip verification
test bench and platform
-
As servo
engineer: Full hardwired Digital Servo Design (focus/tracking/spindle filter,
OPC, auto adjustment algorithm), verified RTL design with equivalent Matlab model and collaborated with verification engineer
-
*Dispatched Sunext Technology in
n
Completed a course of M.S. in
-
Repetitive
Control Algorithm Development for eccentric error compensation of optical servo
n
General purposed MCU (ARM7TDMI) Development
Sep.2000- Aug.2001
-
As SOC Senior Engineer/MTS: Designed fullchip
integration, AMBA system, Memory (SRAM, Flash and SDRAM) management block,
Cache, DMA and peripherals (UART, GPIO, Timer, MCBSP, IIC and etc)
n
Digital Servo Chip
and Algorithm Development
Sep.1995 -Dec. 2000
-
As Servo System
senior engineer: Designed controller and servo specification, researched
stability and coefficient of controller. Analyzed the characteristic of
open/closed loop of servo controller using Matlab and
excel tool. Worked on partitioning of Hardware and Software of Servo controller
considering chip size, flexibility and performance, Divided into Software
digital Servo on DSP, SW/HW Servo Architecture and Full Hardware Servo
Architecture
-
As Servo
engineer: Developed automatic adjustment and track search algorithm using C and
Assemble on ARM7. Designed simple
bus architecture, tracking/focus/sled/spindle servo filter and special
peripherals such as track counter, PWM, timer, interrupt controller. Worked on Block level synthesis, STA, pre/post
simulation, FPGA test, chip test. Made a
proto type FPGA and all function were confirmed. Collaborated with production
FW engineer for launching market
-
*Dispatched
Japan Company in
n
Analog Servo IC Development for CD
player
Aug.1993- Aug. 1995
As analog engineer: Designed Analog Servo, OPAMP and Comparator,
Analog filter, OPAMP application, track search and control logic.
EDUCATION
Ph.D
Mar.
2005 ~ Aug.2008
Ph.D in
Electronics and Computer Engineering (sponsored by Magnachip
Semiconductor and Mewtel Technology Inc.)
-
SOC Design and
Verification in relative with Multimedia and Wireless application
n
Worked on a doctor’s thesis “Design of A
portable surveillance camera system with one-bit motion detection using unified
verification methodology”
n
Technical lead and
management the SOC1 team of ULSI laboratory and team’s project which are MDDI,
MPEG4, SystemC verification platform and Surveillance
Camera project.
n
Initial setup of unified
verification environment and platform
n
Verified surveillance
camera processor using SystemC model and FPAG
platform and Flexible Transform Processor for Multi-Codec (JPEG, MPEG-2,4 and H.264)
on FPGA board with ARM920T
n
Completed surveillance
camera processor development with silicon proven
Master
Sept.2001 ~Aug.2003
Master
Degree in Electrical Engineering (sponsored by Samsung
Electronics Co, LTD)
n
Automatic
Control System for Optical Storage Driver.
n
Thesis
was “ Adaptive repetitive control algorithm for an eccentricity compensation of
optical disk driver”
Mar.1988
~ Aug. 1993
Bachelor
Degree in Electronics Engineering
PUBLICATIONS
- SCI Journal
n A Portable Surveillance
Camera Architecture using One-bit Motion Detection
Jeonghun Kim;
Consumer Electronics, IEEE Transactions on Volume 53,
Issue 4, Nov. 2007 Page(s):1063 – 1068
n An MDDI-Host Architecture
with Low Complexity for SoC Platforms
Consumer Electronics, IEEE Transactions on, Volume 53,
Issue 4, Nov. 2007 Page(s):1668 - 1673
n Track following Control with
DFT Estimator for Eccentric Error Compensation of Optical Disk Driver
Kim, Jeonghun.; Lim, Kusam.; Kim, Suki.;
Consumer Electronics, IEEE Transactions on, Volume 53,
Issue 2, May 2007 Page(s):467 - 473
n The v2.0+EDR Bluetooth SOC architecture for multimedia
Jeonghun Kim; Youngwhan Choi; Jungwon Jeong; Suhho Lee; Suki Kim;
Consumer Electronics, IEEE Transactions on,
Volume 52, Issue 2, May 2006 Page(s):436 - 444,
n Corrections to Adaptive Repetitive
Control for an Eccentricity Compensation of Optical Disk Drivers
Kim, Jeonghun.; Chang, K.;
Shim, Iilju.; Park, Gwitae.;
Kim, Suki.;
Consumer Electronics, IEEE Transactions on, Volume 53,
Issue 3, Aug. 2007, Page(s):962 - 968
- International Conference
n Co-simulation of SystemC TLM with RTL HDL for Surveillance Camera System Verification
ICECS (International
Conference Circuit and Systems), Aug. 2008
n Design an Infrared Wireless Optical Mouse System and a Dual-band Infrared
Receiver
Kyusam Lim, Kon-Woo Kwon,
ICECS (International
Conference Circuit and Systems), Aug. 2008
n A Low Power SOC
Architecture for the v2.0+EDR Bluetooth
Jeonghun Kim, Kusam Lim, Jungwon Jeong, Taesik Bang, Suki Kim;
ICCE (IEEE
International Conference on Consumer Electronics), Jan 2008
n Security camera processor
with one-bit motion detection algorithm
Jeonghun
Kim,
International
SOC Design Conference, Oct, 2007 (Chip Design Contest: Altera
award
n Surveillance Camera SOC
Architecture using One-bit Motion Detection for Portable Application
Jeonghun Kim,
IEEE International SOC Conference, SOC 2007, Sept. 2007,
Page(s): 71-74
n Dynamic Eccentric Error
Compensation for Track Following Control of Optical Disk Driver
Jeonghun Kim; Kyu-sam Lim; Suki Kim;
IEEE International Symposium on Circuits and Systems,
2007, May 2007, Page: 3808 – 3811
n A novel motion
detection pointing device Using a binary CMOS image sensor
Hee Ju Park; Kyung Bum
Kim; Jeong Hun Kim; Suki
Kim;
Circuits and
Systems, IEEE International Symposium on, May 2007, Page(s):837 - 840
n A Low Power
QXGA Camera Signal Processor for
Kyusam Lim; Jeonghun Kim; Hwangyoung
So; Sejin Kang; Suki Kim;
Digest of
Technical Papers. IEEE International Conference on Consumer Electronics, Jan.
2007
n A Platform-based SoC Design
Environments
Jeonghun Kim, Kyeongtae Moon, Jungwon Jeong, Suki Kim;
IPSOC
(IP Based SoC Design conference & Exhibition),
Dec. 2006.
n Integrating Makefile, Tcl and Perl into SoC-based
Design Environments
Jeonghun Kim, Jungwon Jeong, Taesik Bang, Suki Kim;
ICCSC (3rd IEEE
International Conference on Circuits and Systems for Communications), July 2006
n Implementation
of H.264/AVC decoder for mobile video applications
Suh Ho Lee; Jeong Hun
Kim; Ji Hwan Park; Seon Wook Kim; Suki Kim;
IEEE
International Symposium on Circuits and Systems, Proceedings, May 2006.
n A Flexible Transform Processor Architecture for
Multi-Codec (JPEG, MPEG-2,4 and H.264)
Ji
ISCAS (IEEE
International Symposium on Circuits and Systems), May, 2006
n The v2.0+EDR Bluetooth SOC Architecture for Multimedia
Jeonghun Kim, Taehyeon Sim, Youngwhan
Choi, Jungwon Jeong, Taesik Bang, Suki Kim;
ICCE (IEEE
International Conference on Consumer Electronics), Jan 2006
n Programmable Digital Filters for Optical Servo System
Jeonghun. Kim, Iljoo Shim,
and
International Conference on
the Society of Instrument and Control Engineers (SICE), Aug. 2002, pp. 2569-2574
- PATENTS
-
Patent
number
submit-date register-date Title
n US 7,215,608 B2, Jun 9, 2004, May 8, 2007, OPTICAL DISK REPRODUCING APPARATUS FOR COMPENSATING FOR TRACKING ERROR BY USING REAL-TIME REPETITIVE CONTROL AND METHOD OF DRIVING OPTICAL DISK REPRODUCING APPARATUS
n
US 6,714,492 B2, Nov 26, 2001, Mar. 30,2004, OPTICAL DISC PLAYER FOR COMPENSATING FOR ECCENTRICITY ERROR WITH ECCENTRICITY DETECTED AND COMPENSATED AT DIFFERENT PARTS OF THE PLAYER
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Patent number
submit-date register-date Title
n 0416593 2001-0016879 20010330 20040115
Eccentric error compensation of optical disc servo
n 0382735 2001-0010357 20010228 20030421 Lenz
brake algorithm for reduce a access time
n 0224698 1997-0014193 19970417 19990715
Digital filter structure for optical servo
n 1820922 1995-049312 19951213 19981210 Tracking actuator jump voltage generator
of compact disc player