Welcome to Kirill Minkovich's Home Page (graduated, information is outdated)


To Contact Me

Office: Boelter Hall 4651 UCLA Computer Science
Tel: (323) 743-3782 (cell)
E-mail:
Resume: (pdf) (doc)

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Background


Publications

Author list is in alphabetical order by last name (bold denotes primary author)
  1. J. Cong and K. Minkovich, "Optimality Study of Logic Synthesis for LUT-Based FPGAs," Proceedings of the 14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2006.

  2. J. Cong and K. Minkovich, "Optimality Study of Logic Synthesis for LUT-Based FPGAs," TCAD: Special Edition for FPGA, 2006

  3. J. Cong and K. Minkovich, "A Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs," Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2007.

    All the files from this paper! This includes the CNF files, RIMatch source and executable!
  4. J. Cong and K. Minkovich, "Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs," Proceedings of the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2008.

    BTWMap Download link
  5. J. Cong and K. Minkovich, "Logic Synthesis for Better Than Worst-case Designs," International Symposium on VLSI Design, Automation and Test, April 2009.

  6. J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou, "Accelerating Monte-Carlo based SSTA using FPGAs," Proceedings of the 18th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2010.

  7. J. Cong and K. Minkovich, "Logic Synthesis for Better Than Worst-case Architectures," under review.

  8. J. Cong and K. Minkovich, "LUT-Based FPGA Technology Mapping for Reliability," Proceedings of the 2010 Design Automation Conference, June 2010.


Downloads

Useful scripts and other small downloadbles. If you make any usefull changes, be sure to email them to me so I can upload them. Any bugs will be fixed within 2 days!!!

Perl scripts

Benchmark Files

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