Welcome to Kirill Minkovich's Home Page (graduated, information is outdated)

To Contact Me Office: Boelter Hall 4651 UCLA Computer Science Tel: (323) 743-3782 (cell) E-mail: Resume: (pdf) (doc)

Be notified of page updates it's private

Background

• After receiving my B.A. degree in Computer Science from UC Berkeley in 2003, I joined the VLSI CAD Laboratory at the UCLA CS Department in the summer of 2005. I was working under Professor Jason Cong in the field of Logic Synthesis CAD tools for FPGAs. I was also the President of CSGSC at UCLA. I finished my PhD in 2010 and now work at HRL Laboratories as a postdoc.

Publications

1. J. Cong and K. Minkovich, "Optimality Study of Logic Synthesis for LUT-Based FPGAs," Proceedings of the 14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2006.

   • EE Times article about the paper.
     
   • FPGA Journal article about this paper.
     
     

2. J. Cong and K. Minkovich, "Optimality Study of Logic Synthesis for LUT-Based FPGAs," TCAD: Special Edition for FPGA, 2006

3. J. Cong and K. Minkovich, "A Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs," Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2007.

   All the files from this paper! This includes the CNF files, RIMatch source and executable!

4. J. Cong and K. Minkovich, "Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs," Proceedings of the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2008.

   BTWMap Download link

5. J. Cong and K. Minkovich, "Logic Synthesis for Better Than Worst-case Designs," International Symposium on VLSI Design, Automation and Test, April 2009.

6. J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou, "Accelerating Monte-Carlo based SSTA using FPGAs," Proceedings of the 18th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2010.

7. J. Cong and K. Minkovich, "Logic Synthesis for Better Than Worst-case Architectures," under review.

8. J. Cong and K. Minkovich, "LUT-Based FPGA Technology Mapping for Reliability," Proceedings of the 2010 Design Automation Conference, June 2010.

Downloads

Perl scripts

• BLIF to VHDL. (BLIF2VHDL) This Perl script transforms a simple BLIF file into a VHDL file. It transforms LUT and latches. Download
  You might also want to check out University of Hamburg's collection of tools. Link
• BLIF to Verilog. (BLIF2Verilog) This Perl script transforms a simple BLIF file into a Verilog file. It transforms LUT and latches. Download
  
• CNF simplifier. This Perl script simplifies CNFs (a set of clauses in conjunctive normal form). Download
  It does the following things: converts (a|b)&(a|b|c) into (a|b) and it has the code to do resolution but is currently commented out since it creates too many clauses.
• Email address obfuscator This Perl script takes as input an email address and print an HTML javascript obfuscated version so you can paste it into your homepage. It's only 6 lines but it could be a lot shorter. Download or try it out here
                 Email:

Benchmark Files

• BLIF Benchmark suit. This zip file contains the entire MCNC benchmark suit in the BLIF format. These are guaranteed to be functionally original but not structurally (they may have been synthesised before). It also contains every single BLIF benchmark I could find (over 200 distinct benchmarks). If any are missing please send me an email. Download
  For the original circuits, please go to: http://www-lab13.kuee.kyoto-u.ac.jp/eda/benchmark/mcnc/benchmarks/

Google Analytics

• Check out this automatic way to insert the Google Analytics tag into everypage on the fly using Apache and Perl. This way you don't need to edit any HTML, just add the perl script and every requested HTML page will include the correct code block for tacking users.
• Just click here for the Google Analytics page.