Keynote Address I:
Microelectronics Evolution Brings Real Multimedia Era
Title and Copyright
Organizing Committee
Technical Program Committee
Advisory Board
Steering Committee
General Chair's Message
Program Chair's Message
ASP-DAC '97 University LSI Design Contest
Call for Papers
Best Paper Awards
Microelectronics Evolution Brings Real Multimedia Era
1A.1 A Co-evaluation of FPGA Architectures and the CAD System for
Telecommunication
1A.2 A Rapid Prototyping Method for Top-Down Design of System-on-Chip
Devices Using LPGAs
1A.3 Performance Test of Viterbi Decoder for Wideband CDMA System
1B.1 Delay Estimation on Optimization of Logic Circuits: A Survey
1B.2 Delay Estimation for Technology Independent Synthesis
1B.3 Performance and Reliability Driven Clock Scheduling of Sequential Logic
Circuits
1C.1 CBLO: A Clustering Based Linear Ordering Algorithm for Netlist
Partitioning
1C.2 Design Driven Partitioning
1C.3 A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm
1C.4 Acceleration of Mincut Partitioning using Hardware CAD Accelerator
TP5000
Computing Brokerage and Its Applications in VLSI Design
2A.1 A Programmable Application-Specific VLSI Architecture and Implementation
for Speech Word-Recognizer
2A.2 A High Performance FIR Filter Dedicated to Digital Video Transmission
2A.3 An Efficient Hierarchical Clustering Method for the Multiple Constant
Multiplication Problem
2A.4 Structural Approach for Performance Driven ECC Circuit Synthesis
2B.1 Statistical Estimation of Combinational and Sequential
CMOS Digital Circuit Activity Considering Uncertainty of Gate Delay
2B.2 An Entropy Measure for Power Estimation of Boolean Functions
2B.3 An Enhanced Iterative Improvement Method for Evaluating the Maximum
Number of Simultaneous Switching Gates for Combinational Circuits
2B.4 A Power Driven Two-Level Logic Optimizer
2B.5 A Note on the Relationship Between Signal Probability and Switching
Activity
2C.1 Modeling and Layout Optimization of VLSI Devices and Interconnects in
Deep Submicron Design
2C.2 A New Layout-Driven Timing Model for Incremental Layout Optimization
2C.3 Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore
Delay Model for Row Based VLSIs
JavaTM in Electronic Design Automation
3A.1 Polling-based Real-time Software for MPEG2 System Protocol LSIs
3A.2 Synthesis and Analysis of an Industrial Embedded Microcontroller
3A.3 ASAver.1: An FPGA-Based Education Board for Computer Architecture/System
Design
3B.1 Property Verification in the Design of Telecom Applications
3B.2 Verification Methodology of Compatible Microprocessors
3B.3 RTL Verification of Timed Asynchronous and Heterogeneous Systems
using Symbolic Model Checking
3C.1 CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation
Environment for Static CMOS Circuits
3C.2 Power Consumption in CMOS Combinational Logic Blocks at High
Frequencies
3C.3 A New Approach for an AHDL Based on System Semantics
3D.1 EMC-Adequate Design of Printed Circuit Board as a Part of the System
Development
3D.2 Multi-Pride: A System for Supporting Multi-Layered Printed Wiring
Board Design
3D.3 Crosstalk Noise in High Density and High Speed Interconnections
due to Inductive Coupling
CAD Methodology and Business Models for Future Products
4A.1 Embedded Architectural Simulation within Behavioral Synthesis Environment
4A.2 Evaluating Cost-Performance Tradeoffs for System Level Applications
4A.3 A Quantitative Analysis for Optimizing Memory Allocation
4B.1 Concurrent Cell Generation and Mapping for CMOS Logic Circuits
4B.2 Logic Synthesis for Cellular Architecture FPGAs Using BDDs
4B.3 BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT
Architecture
4C.1 General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on
Bounded Slicing Grid Structure
4C.2 A Building Block Placement Tool
4C.3 VEAP: Global Optimization based Efficient Algorithm for VLSI Placement
4C.4 An Improved Objective for Cell Placement
4D.1 HK386: An x86-Compatible 32bit CICS Microprocessor
4D.2 Super Low Power 8-bit CPU with Pass-Transistor Logic
4D.3 A Functional Memory Type Parallel Processor for Vector Quantization
4D.4 High Speed Bit-Serial Parallel Processing on Array Architecture
4D.5 Self-Timed 1-D ICT Processor
4D.6 A Real-Time High Performance Edge Detector for Computer Vision
Applications
4D.7 An LSI Implementation of the Simple Serial Synchronized Multistage
Interconnection Network
4D.8 The DRT Network Router Chip
4D.9 Single Cycle Access Cache for the Misaligned Data and Instruction Prefetch
4D.10 VLSI Implementation of a Real-time Operating System
4D.11 A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under
500ps
4D.12 A Current Mode Cyclic A/D Converter with a 0.8um CMOS Process
4D.13 A Current-mode,3V,20MHz, 9-bit equivalent CMOS Sample-and-Hold
Circuit
5A.1 Hardware-Software Co-design: Tools for Architecting Systems-On-A-Chip
5A.2 Trade-off Evaluation in Embedded System Design Via Co-simulation
5A.3 A Transformational Codesign Methodology
5B.1 A Testability Analysis Method for Register-Transfer Level Descriptions
5B.2 Non-Scan Design for Testable Data Paths Using Thru Operation
5B.3 Block-Level Fault Isolation Using Partition Theory and Logic Minimization
Techniques
5B.4 The Use of Hierarchical Information to Test Large Controllers
5B.5 Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD
Layout Data in the CAD-linked EB Test System
5C.2 Monte Carlo Simulation for Single Electron Circuits
5C.3 Parallel Calculation of 3-D Parasitic Resistance and Capacitance
with Linear Boundary Elements
5C.4 Simulation of Gate Switching Characteristics of a Miniaturized MOSFET
based on a Non-Isothermal Non-Equilibrium Transport Model
Presented by :
5D.1 The EUROPRACTICE MPC Service
5D.2 Multi-Project Chip Activities in Korea-IDEC Perspective-
5D.3 Multi-Project Chip Service for University and Industry in Taiwan
5D.4 VLSI Design and Education Center (VDEC) Current Status and Future Plan
6A.1 Choosing a Digital Simulator
6A.2 A Hardware/Software Co-simulation Environment for Micro-processor
Design with HDL Simulator and OS interface
6A.3 VIDE: A Visual VHDL Integrated Design Environment
6A.4 Advanced Processor Design using Hardware Description Language AIDL
6B.1 Adaptive Models for Input Data Compaction for Power Simulators
6B.2 Fuzzy-based Circuit Partitioning in Built-in Current Testing
6B.3 Reducing the Complexity of Path Classification by Reconvergence Analysis
6B.4 Modelling and Detection of Dynamic Errors due to Reflection - and
Crosstalk-Noise
6B.5 Fault Coverage Improvement Based on Error Signal Analysis
6C.1 Low-Power Multiple-Valued Current-Mode Integrated Circuit with
Current-Source Control and Its Application
6C.2 Analysis and Design of Multiple-Bit High-Order E-^ Modulator
6C.3 Optimal Loop Bandwidth Design for Low Noise PLL Applications
6C.4 +-1.5V CMOS Four-Quadrant Multiplier
Panelist :
Some Thoughts on Process Retargettable and Reusable IC Intellectual
Property
7A.1 ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup
Table Based FPGAs for High Level Applications
7A.2 Bit-Serial Pipeline Synthesis and Layout for Large-Scale Configurable
Systems
7A.3 An Optimal Scheduling Method for Parallel Processing System of Array
Architecture
7B.1 AQUILA: An Equivalence Verifier for Large Sequential Circuits
7B.2 On the Representational Power of Bit-Level and Word-Level Decision
Diagrams
7B.3 Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms
7B.4 On Properties of Kleene TDDs
7C.1 A Time-Domain Method for Numerical Noise Analysis of Oscillators
7C.2 A New Linear-Time Harmonic Balance Algorithm for Cyclostationary
Noise Analysis in RF Circuits
7C.3 Enhancement of Parallelism for Tearing-based Circuit Simulation
Design and Test of Processor-Core Based Sytems
8A.1 Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
8A.2 A Constructive Method for Data Path Area Estimation During High-Level VLSI
Synthesis
8A.3 RT Level Power Analysis
8A.4 Statistical Design of Macro-models For RT-level Power Evaluation
8B.1 AND/OR Reasoning Graphs for Determining Prime Implicants in
Multi-Level Combinational Networks
8B.2 Efficient Synthesis of AND/XOR Networks
8B.3 An Optimization of AND-OR-EXOR Three-level Networks
8B.4 A New Description of CMOS Circuits at Switch-Level
8C.1 A 2-Dimensional Transistor Placement for Cell Synthesis
8C.2 DP-Gen: A Datapath Generator for Multiple-FPGA Applications
8C.3 A Simultaneous Placement and Global Routing Algorithm with Path
Length Constraints for Transport-Processing FPGAs
8C.4 Not Necessarily More Switches More Routability
Panel : EDA Standardization including CHDS
Moderator : Hitoshi Yoshizawa, NEC
Organizer: Hisakazu Edamatsu, Matsushita Electric Industrial
Panel: The Role of Design Standardization in future complex design
9A.1 On the Control-subroutine Implementation of Subprogram Synthesis
9A.2 A Procedure for Software Synthesis from VHDL Models
9A.3 Built-in Chaining: Introducing Complex Components into Architectural
Synthesis
9B.1 BDD-based Logic Partitioning for Sequential Circuits
9B.2 Cube-Embedding Based State Encoding for Low Power Design
9B.3 On Synthesis of Speed-Independent Circuits at STG Level
9C.1 A Mapping from Sequence-Pair to Rectangular Dissection
9C.2 Solving Constrained Via Minimization by Compact Linear Programming
9C.3 Efficient Routability Checking for Global Wires in Planar Layouts
9C.4 Topological Routing Path Search Algorithm with Incremental Routability
Test
VHDL Analog and Mixed-Signal Extensions Through Examples