Design of High Complexity Superscalar Microprocessor with the Portable IDPS
ASIC Library
A. Greiner, L. Lucas, F. Wajsbürt, and L. Winckel
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads T. Michel, R. Leveugle, G. Saucier, R. Doucet, and P. Chapier
Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations S.-H. Huang and J.M. Rabaey
Instruction-Set Matching and Selection for DSP and ASIP Code Generation
C. Liem, T. May, and P. Paulin
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits S. Gai, P.L. Montessoro, and M. Sonza Reorda
A Functional Approach to Delay Faults Test Generation for Sequential Circuits F. Fummi, D. Sciuto, and M. Serra
ICM2 IC: A New ATM Switching Element for 2.48 Gb/s Communications F. Calvo, P. Plaza, and P. Mateos
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array
R. van Dongen and V. Rikkink
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog
Front End
D. Gevaert, J. Vanneuville, J. Nedved, and J. Sevenhans
Introduction of Permissible Bridges with Application to Logic Optimization afterTechnology Mapping
B. Rohfleisch and F. Brglez
High-Level Synthesis of Digital Circuits by Finding Fixpoints
L. Ghatraju, M.H. Abd-El-Barr, and C. McCrosky
FPGA Partitioning For Critical Paths
D. Brasen And G. Saucier
Signature Analysis for Sequential Circuits with Reset A. P. Stroele
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST I.G. Harris and A. Orailoglu
A Fragmented Register Architecture and Test Advisor for BIST
R.J. Illman and D.J. Traynor
A State Space Decomposition Algorithm for Approximate FSM Traversal H. Cho, G.D. Hachtel, E. Macii, M. Poncino, and F. Somenzi
An OBDD-Representation of Statecharts J. Helbig and P. Kelb
Panel: J. Benkoski, SGS-Thomson Microelectronics, France P. Bricaud, Compass Design Automation, France S. Hamacher, Mentor Graphics, Germany D. Laurent, BULL SA, France W. Ries, Siemens AG-Semiconductor Group, Germany W. Stronski, Cadence Design Systems, Germany P. van Staa, Robert Bosch GmbH, Germany
Modeling of Broken Connections Faults in CMOS ICs M. Favalli, M. Dalpasso, P. Olivo, and B. Riccò
Generating Test Patterns for Bridge Faults in CMOS ICs B. Chess and T. Larrabee
A Hierarchical Approach to Fault Collapsing R. Hahn, R. Krieger, and B. Becker
State Minimization of Pseudo Non-Deterministic FSMs Y. Watanabe and R.K. Brayton
Nondeterministic Finite-State Machines and Sequential Don't Cares M. Damiani
An Extended OBDD Representation for Extended FSMs M. Langevin and E. Cerny
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi
Random Testing of Interconnects in a Boundary Scan Environment
C. Su
Boundary Scan Testing Combined with Power Supply Current Monitoring M. Kärkkäinen, K. Tiensyrjä, and M. Weissenfelt
PLFP256: A Pipeline Fourier Processor
F. Pogodalla and P. Coulomb
A VLSI Implementation of Parallel Fast Fourier Transform
A. Vacher, M. Benkhebbab, A. Guyot, T. Rousseau, and A. Skaf
Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network
D. Jacquet and G. Saucier
Transforming Linear Systems for Joint Latency and Throughput Optimization M.B. Srivastava and M. Potkonjak
Genesis: A Behavioral Synthesis System for Hierarchical Testability S. Bhatia and N.K. Jha
A Synthesis Method for Mixed Synchronous/Asynchronous Behavior T.-Y. Wu, T.-C. Tien, A.C.-H. Wu, and Y.-L. Lin
BIST Test Pattern Generators for Stuck-Open and Delay Testing
C.-A. Chen and S.K. Gupta
Synthesis of Delay-Verifiable Two-Level Circuits W. Ke and P. R. Menon
Synthesis of Sequential Machines with Reduced Testing Cost S.-J. Wang
An Algorithm for Generation of Behavioral Shape Functions
N.D. Holmes and D.D. Gajski
Optimal Operation Scheduling Using Resource Lower Bound Estimations
M.E. Dalkilic and V. Pitchumani
Optimization of Address Generator Hardware
D.M. Grant, J. van Meerbergen, and P.E.R. Lippens
Towards Incorporating Device Parameter Variations in Timing Analysis
M. Sivaraman and A.J. Strojwas
A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation J. Frößl and T. Kropf
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling C. Safinia, R. Leveugle, and G. Saucier
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing
M. Sachdev
Test of Bridging Faults in Scan-Based Sequential Circuits
E. Isern and J. Figueras
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT
R. McGowen and F.J. Ferguson
Interface Controller Synthesis from Requirement Specifications
F. Korf and R. Schlör
Synthesis of System-Level Bus Interfaces
S. Narayan and D.D. Gajski
Panel: K. Baker, Philips, The Netherlands R. Camposano, Synopsys, US F. Cathoor, IMEC, Belgium B. Courtois, INPG/TIMA, France T. Gheewala, CrossCheck, US Y. Zorian, AT&T, US
On Design Rule Correct Maze Routing
E.P. Huijbregts, J.T.J. van Eijndhoven and J.A.G. Jess
An Efficient Router for 2-D Field Programmable Gate Arrays
Y.-L. Wu and M. Marek-Sadowska
Cell Height Driven Transistor Sizing in a Cell Based Module Design
H.-R. Lin, C.-L. Chou, Y.-C. Hsu, and T.-T. Hwang
Non-Tree Routing
B.A. McCoy and G. Robins
Panel: D. Langlois, MISIL Technologies, France A.T. Sauer, SNI, Germany O. Rønning, Nordic VLSI, Norway W. Rehr, IAM, Germany R.L. van der Valk, Bureau van der Valk, The Netherlands A.D. Milne, Wolfson Microelectronics Ltd., UK
Probability Analysis for CMOS Floating Gate Faults
H. Xue, C. Di, and J.A.G. Jess
M-Testability: An Approach for Data-Path Testability Evaluation
M. Jamoussi and B. Kaminska
Interactive System-Level Partitioning with PARTIF T.B. Ismail, K. O'Brien, and A. Jerraya
A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems M. Edwards and J. Forrest
High-Level Design Validation Using Algorithmic Debugging J. Naganuma, T. Ogura, and T. Hoshino
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization F. Depuydt, W. Geurts, G. Goossens, and H. De Man
Scheduling with Environmental Constraints Based on Automata Representations J.C.-Y. Yang, G. De Micheli, and M. Damiani
Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures K. Schoofs, G. Goossens, and H. De Man
Efficient Path Identification for Delay Testing - Time and Space Optimization H. Wittmann and M. Henftling
Effectiveness of a Variable Sampling Time Stategy for Delay Fault Diagnosis
D. Dumas, P. Girard, C. Landrault, and S. Pravossoudovitch
Gate-Delay Fault Test with Conventional Scan-Design A. Kunzmann and F. Böhland
A Graphical Approach to Analogue Behavioural Modelling V. Moser, P. Nussbaum, H.P. Amann, L. Astier, and F. Pellandini
An Overview of Analogue Optimisation Using “AD-OP
T”
E. Byrne, O. McCarthy, D. Lucas, and B. Donnellan
A Reduced-Swing Data Transformation Scheme for Resistive Bus Lines in VLSIs
M. Ikeda and K. Asada
Variable Accuracy Device Modeling for Event-Driven Circuit Simulation
K.W. Michaels and A.J. Strojwas
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits
J.-H. Wang, J.-T. Fan, and W.-S. Feng
An Efficient Yield Optimization Method Using a Two Step Linear Approximation of Circuit Performance
Z. Wang and S.W. Director
Synthesis of Self-Testable Controllers S. Hellebrand and H.-J. Wunderlich
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability T. Kim, K.-S. Chung, and C.L. Liu
Automatic Synthesis of BISTed Data Paths from High Level Specification M.L. Flottes, D. Hammad, and B. Rouzeyre
Flow Management Requirements of a Test Harness for Testing the Reliability of
an Electronic CAD System
G. Bartels, P. Kist, K. Schot, and M. Sim
Distributed Computing, Automatic Design, and Error Recovery in the Ulysses II Framework
S.Parikh, M.L. Bushnell, J. Sienicki, and R. Ganesh
Timing Analysis of Combinational Circuits Using ADD's R.I. Bahar, H. Cho, G.D. Hachtel, E. Macii, and F. Somenzi
Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization
B. Wurth and N. Wehn
Clean Formal Semantics for VHDL P.T. Breuer, L. Sánchez Fernández, and C. Delgado Kloos
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path K. Schneider, T. Kropf, and R. Kumar
"Underground Capacitors" - Very Efficient Decoupling for High Performance UHF Signal Processing ICs T. Johansson, L. R. Virtanen and J.M. Gobbi
Design of a Real Time Geometric Classifier
M. Robert, S. Turgis, P. Gorria, and J. Mitéran
From Behavioral Description to Systolic Array Based Architectures
A. Balboni, C. Costi, F. Fummi, and D. Sciuto
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits
A. Abderrahman, B. Kaminska, and Y. Savaria
AREAL: Automated Reasoning Expert for Analog Layout
H.H. Ahmad and R.J. Mack
An Optimizable Model for Process Independent Symbolic Design
J.-C. Dufourd and J.-F. Naviner
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning W.C. Wu, C.L. Lee, J.E Chen and W.Y. Lin
A Suggestion for Accelerating the Analog Fault Simulation W. Vermeiren, B. Straube, and G. Elst
Software Implementation and Statistical Optimization of Some Electronic Components Lifetime K.C. Kouakou
Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters
A. Boni, G. Chiorboli, G. Franco, S. Mazzoleni, and M. Ostacoli
A Model-Based Approach to Analog Fault Diagnosis Using Techniques from Optimization
S. Ahmed, P.Y.K. Cheung, and P. Collins
Functional Tests for Ring-Address SRAM-Type FIFOs
A.J. van de Goor, I. Schanstra, and Y. Zorian
Testability of Circuits Derived from Functional Decision Diagrams B. Becker and R. Drechsler
A Redefinable Symbolic Simulation Technique to Testability Design Rules
Checking
O. Florent, A. Greiner, M. Hirech, and E. Rejouan
Multilevel Logic Synthesis of Very High Complexity Circuits
L. Burgun, N. Dictus, A. Greiner, E. Pradho, and C. Sarwary
Signal Transition Graph Transformations for Initializability S. Banerjee, R.K. Roy, S.T. Chakradhar, and D.K. Pradhan
Synthesis of Applications-Specific Multiprocessor Systems
M.K. Dhodhi, I. Ahmed, and C.Y.R. Chen
Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations P. Zepter and T. Grötker