SESSION INDEX ED&TC '95
Session 1A: DSP and Multimedia
Session 1B: Mixed-Signal DFT
Session 1C: Exact Methods in Architectural Timing Optimization
Session 2A: Circuit Partitioning
Panel Session 2B: ATE Is Dead Long Live Automated Test
Session 2C: Combinational Logic Synthesis
Session 3A: Designs and Tools for Analogue and Mixed Signal ICs
Session 3B: Memory Testing
Session 3C: Sequential Logic Synthesis
Session 4A: High Speed Telecom Design
Session 4B: System Synthesis
Session 4C: Advanced DFT Techniques
Session 5A: Digital and System Simulation
Session 5B: Code Generation
Session 5C: Sequential ATPG and Diagnosis
Session 6A: CAD Frameworks
Panel Session 6B: Simulation Versus formal Verification
Session 6C: Test Generation and Testability
Session 7A: Applications of Symbolic Traversal Techniques
Session 7B: Handling Physical Constraints in Architectural Synthesis
Session 7C: Self-Checking Approaches
Session 8A: Design Methodologies
Session 8B: Power and Delay Issues in Logic Synthesis
Session 8C: BIST Methodologies
Session 9A: New Developments in Logic Representation and Verification Techniques
Panel Session 9B: Can Mixed Signal Re-Vitalise European Microelectronics Industry?
Session 9C: Test Preparation for Mixed-Signal Systems
Session 10A: Hierarchical Layout
Session 10B: Modeling and Design of ASIPs
Session 10C: Delay Testing and Diagnosis
Session 11A: New Applications of Analogue Simulation Algorithms
Session 11B: Design Problems in Pipelines
Session 11C: IDDQ Testing
Poster Session