Three applications are presented with a common theme of improved performance solving real problems in the DSP, image processing and graphics presentation areas
A Prototype VLSI Chip Architecture for JPEG Image Compression
M. Kovac, N. Ranganathan, and M. Zagar
A Variant of Cooley-Tuckey Algorithm with Local Memory Management
J.-M. Bourguet, T. Nancy, S. Wei, J. Leroy and R.G. Crappe
Eliminating the Z-Buffer Bottleneck
G. Knittel and A. Schilling
Defect-oriented DFT methodology. DFT structure. On-Line DFT from IC’s to Boards.
Defect Oriented Test Methodology for Complex Mixed-Signal Circuits
F.C.M. Kuijstermans, A.P. Thijssen, and M. Sachdev
A Design-for-Test Structure for Optimising Analogue and Mixed Signal IC Test
A.H. Bratt, A.M.D. Richardson, R.J. Harvey, and A.P. Dorey
Mixed-Signal Circuits and Boards for High Safety Applications
M. Lubaszewski, V. Kolarik, S. Mir, C. Nielsen, and B. Courtois
The first two papers in this Session describe exact methods for scheduling using bipartite matching and symbolic techniques, respectively. The third paper describes an exact architectural optimisation approach.
Exact Scheduling Strategies Based on Bipartite Graph Matching
A.H. Timmer and J.A.G. Jess
On Applicability of Symbolic Techniques to Larger Scheduling Problems
I. Radivojevic and F. Brewer
Optimizing Synchronous Systems for Multi-Dimensional Applications
N.L. Passos, E.H.-M. Sha, and L.-F. Chao
Circuit partitioning is a fundamental problem in VLSI design. In this Session, the first paper presents a new metric for multi-way circuit partitioning. The last two papers present new approaches to partitioning for MCM and FPGA designs.
When Clusters Meet Partitions: New Density-Based Methods for Circuit Decomposition
D.J.-H. Huang and A.B. Kahng
Circuit Clustering for Delay Minimization Under Area and Pin Constraints
H. Yang and D.F. Wong
Architecture Driven K-Way Partitioning for Multichip Models
B.M. Riess and A.A. Schoene
With the advent of open system architectures like VXI and open software platforms, e.g. LabVIEW, the traditional ATE business is likely to change significantly over the next few years. Rather than buying large general purpose test systems, the market may prefer to choose tailored, optimised systems, often rather low-cost, based upon open concepts. In such systems the test functionality is largely provided by the software. Hence, the traditional ATE may be dying and the market change to automated test rather than ATE. The question for many is: “Will this happen, when will it happen, and who will be the major players?”
The first paper proposes a new method to synthesize circuits tolerant for single stuck-at faults. A novel approach to BDD-based Boolean matching is presented in the second paper. The last paper describes a polynomial algorithm for the minimization of Reed-Muller expressions.
Synthesis of Multilevel Fault-Tolerant Combinational Circuits
A. Bogliolo and M. Damiani
Improved Technology Mapping Using a New Approach to Boolean Matching
B. Kapoor
Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions
R. Drechsler and B. Becker
Analogue and mixed signal integrated circuits with emphasis on low power and switched current design approaches are presented together with synthesis tool for analogue modules.
Low-Voltage Low-Power Switched-Current Circuits and Systems
N. Tan and S. Eriksson
Low Supply Voltage, Low Noise Fully Differential Programmable Gain Amplifiers
A. Pletersek, D. Strle and J. Trontelj
A Universal Telephone Audio Circuit with Loudhearing and Handsfree Operation in CMOS Technology
K. Hayat-Dawoodi, O. Alminde, V. Kunc, and M. Pauritsch
A Flexible Topology Selection Program as Part of an Analog Synthesis System
P. Veselinovic, D. Leenaerts, W. van Bokhoven, F. Leyn, F. Proesmans, G. Gielen, and W. Sansen
The first two papers present new algorithms for testing word-oriented DRAMs and shifting-type FIFOs respectively. The last paper deals with a practical implementation of a very high speed BISTed SRAMs and CAMs.
Pseudo-Exhaustive Word-Oriented DRAM Testing
M.G. Karpovsky, V.N. Yarmolik, and A.J. van de Goor
Functional Test for Shifting-Type FIFOs
A.J. van de Goor, I. Schanstra, and Y. Zorian
A 370-Mhz Memory Built-in Self-Test State Machine
R.D. Adams, J. Connor, G.S. Koch, and L. Ternullo, Jr.
Three papers are presented in this Session on modeling and synthesis of sequential circuits. The first paper describes a new model for the representation and optimization of hierarchical synchronous circuits. The second paper addresses the initialization problem in retiming. The third paper presents a new FGM encoding algorithm that avoids sequential false paths.
Modeling and Optimization of Hierarchical Synchronous Circuits
B. Lin, G.G. de Jong and T. Kolks
Improving Initialization Through Reversed Retiming
L. Stok, I. Spillinger, and G. Even
Elimination of Multi-Cycle False Paths by State Encoding
Z. Hasan and M.J. Ciesielski
This Session discusses new architectures and design techniques for advance high speed telecom systems. ECL and mixed ECL/CMOS designs will be presented and discussed.
Input and Output Processor for an ATM High Speed Switch (2.5 gb/s): The CMC
P. Plaza, J.C. Diaz, F. Calvo, L. Merayo, M. Zamboni, P. Scarfone, and M. Barbini
Post-Layout Optimization of Power and Timing for ECL LSIs
A. Onozawa, K. Kawai, and H. Kitazawa
A 622/155 Mbps ATM Line Terminator Mono-Chip
M. Diaz Nava, D. Belot, P. Delerue, and J. Bulone
This Session is about modeling and synthesis for embedded systems. The first two papers discuss new specification models and their use in simulation and hardware/software codesign. The last paper presents a software scheduling technique for concurrent real-time systems.
A Unified Model for Co-Simulation and Co-Synthesis of Mixed Hardware/Software Systems
C.A. Valderrama, A. Changuel, P.V. Raghavan, M. Abid, T. Ben Ismail, and A.A. Jerraya
SLIF: A Specification-Level Intermediate Format for System Design F. Vahid and D. Gajski
Deadline-Monotonic Software Scheduling for the Co-Synthesis of Parallel Hard Real-Time Systems
P. Altenbernd
Advanced algorithmic and high level techniques are applied to problems in synthesis, minimization and on-chip test pattern generation.
High-Level Synthesis for Easy Testability
M.L. Flottes, D. Hammad, and B. Rouzeyre
Sequential Logic Minimization Based on Functional Testability
F. Fummi, D. Sciuto, and M. Serra
A Gauss-Elimination Based PRPG for Combinational Circuits
L.-R. Huang, S.Y. Kuo, and I.-Y. Chen
In the first paper mixed signal simulation capabilities of VHDL for system-on-chip applications are demonstrated. The second contribution presents a new concept to implement event monitors. The third paper discusses novel delay-models for sea-wire arrays.
Mixed-Signal Modeling in VHDL for System-On-Chip Applications
F. Pichon, S. Blanc, and B. Candaele
Run-Time Consistency Checking in Discrete Simulation Models
J.W.G. Fleurkens, C.A.J. van Eijk, and J.A.G. Jess
Delay Models for the Sea-of-Wires Array Synthesis System
I.-Y. Chen, G.L. Chen, and S.-Y. Kuo
Code generation for embedded instruction-set processors is a topic of growing importance, especially in the field of DSP. In this Session new techniques and models are presented for code generation. The first and third paper focus on scheduling issues. The second paper discusses instruction extraction from processor netlists.
A Unified Scheduling Model for High-Level Synthesis and Code Generation
A. Kifli, G. Goosens, and H. De Man
A BDD-Based Frontend for Retargetable Compilers
R. Leupers and P. Marwedel
Efficient Code Generation for In-House DSP-Cores
M.T.J. Strik, J.L. van Meerbergen, A.H. Timmer, J.A.G. Jess, and S. Note
The first paper identifies a new structural attribute for evaluating complexity of sequential ATPG. Sequential ATPG for circuits without next states or synchronizing sequences is proposed in the second paper. The last paper presents the use of genetic algorithms in diagnosing very large sequential circuits.
Complexity of Sequential ATPG
T.E. Marchok, W. Maly, A. El-Maleh, and J.Rajski
Improved Sequential ATPG Using Functional Observation Information and New Justification Methods
J. Park, C. Oh, and M.R. Mercer
GARDA: A Diagnostic ATPG for Large Synchronous Sequential Circuits
F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda
The first two papers in this Session discuss CAD framework support for configuring and executing design projects. The last paper presents results of coupling two complementary CAD frameworks.
Controlling Change Propagation and Project Policies in IC Design
Y. Mathys, S. Soudagar and M. Morgan
Generic Design Flows for Project Management in A Framework Environment
E. Kwee-Christoph, F. Feldbusch, R. Kumar, and A. Kunzmann
Enhanced Functionality by Coupling the JESSI-COMMON-Framework with an ECAD Framework
R. Seepold and A. Kunzmann
Will formal verification substitute simulation? What are the forseen roles of heavy simulation or emulation versus formal verification in system design? Will solutions come from the traditional CAD vendors? And is there a chance to see formal verification successfully applied in mixed signal design in a reasonable time?
The first paper addresses the problem of test quality obtained by using unbiased testing. The second one proposes a new approach to compute testability of a VLSI circuit in a hierarchical design environment. The last contribution deals with delay fault test pattern generation for sequential circuits.
Enhanced Testing Performance Via Unbiased Test Sets
L.-C. Wang, M.R. Mercer, and T.W. Williams
A Testability Measure for Hierarchical Design Environments
M.H.C. Lee and D.L. Tao
Gate Delay Fault Test Generation for Non-Scan Circuits
G. van Brakel, H.G. Kerkhoff, U. Gläser, and H.T. Vierhaus
Recent applications of BDD-based symbolic traversal techniques to MOS-circuits, graph algorithms, asynchronous circuits, process calculi are presented.
Verifying Real-Time Properties of MOS-Transistor Circuits
J. Froßl and Th. Kropf
Using Symbolic Techniques to Find the Maximum Clique in Very Large Sparse Graphs
F. Corno, P. Prinetto, and M. Sonza Reorda
Checking Signal Transition Graph Implementability by Symbolic BDD Traversal
A. Kondratyev, J. Cortadella, E. Pastor, O. Roig, M. Kishinevsky, and A. Yakovlev
Proving Testing Preorders for Process Algebra Descriptions
F. Corno, M. Cusinato, M. Ferrero, and P. Prinetto
Modern technologies require physical constraints to be taken care of at early stages of the design process. The first paper addresses the inclusion of memory accesses in the timing and allocation steps for data paths. Secondly, we deal with the problem of switching between libraries at late stages of the design. Finally, the problems of planning the clock distribution at architectural level are dealt with.
Architectural Exploration for Datapaths with Memory Hierarchy
N.D. Holmes and D.D. Gajski
Design Reuse Through High-Level Library Mapping
P.K. Jha and N.D. Dutt
Automatic Clock Tree Generation in ASIC Designs
A. Balboni, C. Costi, A. Pellencin, M. Quadrini, and D. Sciuto
The Session concerns concurrent error detection techniques including self-checking implementations for RAMs and FFT as well as off-line and/or concurrent checking for bridging and parametric faults based on intermediate voltage monitoring.
Area Versus Detection Latency Trade-offs in Self-Checking Memory Design
O. Kebichi, M. Nicolaidis, and Y. Zorian
Self-Checking Architectures for Fast Hartley Transform
J.M. Tahir, S.S. Dlay, R.N. Gorgui-Naguib and O.R. Hinton
Built-in Intermediate Voltage Testing for CMOS
J.-J. Tang, K.-J. Lee, and B.-D. Liu
This Session discusses the advanced design and test methods that are applied during the implementation of a powerful superscalar processor, a real time image processing application and a prototype of a SIMD processor.
Design and Test of the PowerPC™ 603 Microprocesso
E.K. Vida-Torku, S. Park, R. Reed, and C.H. Malley
An ASIC Design for Real-Time Image Processing in Industrial Applications
M. Valle, G. Nateri, D.D. Caviglia, G.M. Bisio, and L. 3rio
Rapid Prototype of a Hardware Emulator for a SIMD Processor Array
D.L. Andrews, A. Wheeler, B. Wealand, and C. Kancler
Power and delay are closely related to each other. Delay estimates are needed to minimise useless power dissipation (glitches). Power dissipation can also be optimised by minimising the switching activity by appropriate decomposition of logic functions.
Analysis and Reduction of Glitches in Synchronous Networks
J.A.J. Leijten, J. van Meerbergen, and J.A.G. Jess
Decomposition of Logic Functions for Minimum Transition Activity
R. Murgai, R.K. Brayton, and A. Sangiovanni-Vincentelli
Prediction of Interconnect Delay in Logic Synthesis
H.-F. Jyu and S. Malik
This Session discussed advanced BIST methodologies which target delay, stuck-open and random-pattern resistant faults.
A BIST Approach to Delay Fault Testing with Reduced Test Length
B. Wurth and K. Fuchs
BIST Hardware Generator for Mixed Test Scheme
C. Dufaza, H. Viallon, and C. Chevalier
Accumulator-Based BIST Approach for Stuck-Open and Delay Fault Testing
I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis
The first paper analyses decision diagrams. The second paper applied learning techniques in verifying combinational circuits. The third paper extends BDDs.
How Many Decomposition Types Do We Need?
B. Becker and R. Drechsler
VERIFUL: VERification Using FUnctional Learning
R. Mukherjee, J. Jain, and M. Fujita
Implicit Manipulation of Polynomials Using Zero Suppressed BDD
S. Minato
Panelists:
J.-P. Dauvin, SGS-Thomson Microelectronics, France, B. Pruniaux; ES2, France, P. van Staa; R.
Bosch GmbH, Germany, W. Sansen, Katholieke Univ. Leuven, Belgium, and E.P.C. van Utteren,
Philips Research Labs, The Netherlands
The European microelectronics industry has been lagging behind that of the USA and Japan for a number of years. However, the growing use of mixed signal seems to be a vital opportunity for the European microelectronics industry to fight back, since the application field of mixed signal is one where Europe already has a strong foothold with its dominance in telecommunications, automotive electronics, consumer electronics, military electronics and industrial control applications. The panel will assess the current situation, explain what a strong European microelectronics industry in this field means to the user community, and give their views on the options for Europe to improve the current situation.
Testing analogue and digital simultaneously. Fault extraction and simulation in analogue ICs. Pragmatic approach for test programme generation in mixed-signal systems.
Automatic Test Vector Generation for Mixed-Signal Circuits
B. Ayari, N. Ben Hamida, and B. Kaminska
Automatic Fault Extraction and Simulation of Layout Realistic Faults for Integrated Analogue Circuits
C. Sebeke, M.J. Ohletz, and J.P. Teixeira
Achieving Simulation-Based Test Program Verification and Fault Simulation Capabilities for Mixed-Signal Systems
P. Caunegre and C. Abraham
This Session addresses hierarchical methods in layout synthesis. The first paper describes the influence of restricted pin positions on the cell area during top-down chip planning. The other two papers focus on EMC-driven midway routing and on hierarchical multi-layer global routing combining top-down and bottom-up routers.
The Effect of Pin Constraints on Layout Area
B. Schürmann and J. Altmeyer
EMC-Driven Midway Routing On PCBs
H. Schmidt, D. Theune, R. Thiele, and T. Lengauer
A Hybrid Hierarchical Approach for Multi-Layer Global Routing
M. Hayashi and S. Tsukiyama
This Session is concerned with the design and use of application-specific instruction-set processors (ASIPs). The first paper discusses high-level metrics for software running on programmable processors. The second paper introduces a processor model. The third paper presents a methodology for ASIP design.
Software Estimation Using a Generic-Processor Model
J. Gong, D.D. Gajski, and S. Narayan
Describing Instruction Set Processors Using nML
A. Fauth, J. Van Praet, and M. Freericks
Incorporating Compiler Feedback Into The Design of ASIPs
F. Onion, A. Nicolau, and N. Dutt
This Session deals with new algorithms for exact computation of path delay fault coverage for large combinational circuits as well as robust and non-robust test pattern generation. Problems of diagnosis of delay faults in synchronous sequential circuits are also addressed.
An Efficient Method for Computing Exact Path Delay Fault Coverage
B. Kapoor
BIT Parallel Test Pattern Generation for Path Delay Faults
M. Henftling and H. Wittmann
A Trace-Based Method for Delay Fault Diagnosis in Synchronous Sequential Circuits
P. Girard, C. Landrault, S. Pravossoudovitch, and B. Rodriguez
The first paper presents a powerful mathematical approach for computation of a rational transfer function (applied on inductance calculation). In the second paper a Simulation Control Language and System is described. In the third paper the three-dimensional thermal equivalent circuit is presented.
Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures
L.M. Silveira, M. Kamon, and J. White
On Software Development to Support Statistical Simulation of Analogue Circuits
E. Driouk, O. Jarov, and A. Sukhodolsky
Multilevel Thermal Simulation of MCMs by System “MONSTR-M
”
V.A. Koval and D.V. Fedasyuk
Pipeline schedules enable various new optim3zations, especially when combined with speculative execution. However, dangers of hazards have to be considered. An extension of path based scheduling makes it more effective for pipelines.
Combining MBP-Speculative Computation and Loop Pipelining in High-Level Synthesis
U. Holtmann and R. Ernst
PPS: A Pipeline Path-Based Scheduler
M. Rahmouni and A.A. Jerraya
Balancing Structural Hazards and Hardware Cost of Pipelined Processor
A.E. Casavant
In this Session the design problems of IDDQ sensors are covered and also the automatic synthesis of current testable circuits is addressed.
Correlation Between IDDQ Testing Quality and Sensor Accuracy
M. Dalpasso, M. Favalli, and P. Olivo
Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors
H.-J. Wunderlich, M. Herzog, J. Figueras, J. Carrasco, and A. Calderón
A Built-in Quiescent Current Monitor for CMOS VLSI Circuits
A. Rubio, J. Figueras, D. Mateo, J. Segura, E. Janssens, H. Casier, and P. DePauw
TRJM: A High Speed Programmable ATM-SDH Mapper
J. Crespo, F. Calvo, J.I. Solana, R. Caravantes, and J.L. Conesa
Artificial Neural Networks in Medical Decision Making Systems: An Application to Pulmonary Diseases Diagnosis Through VHDL Synthesis
G.-P. Economou, J.A. Hallas, E.P. Mariatos, and C.E. Goutis
Integration of an Expert System for Analogue Layout Synthesis into a Commercial CAD Framework
D.A. Bensouiah, R.J. Mack, and R.E. Massara
Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
B. Becker and R. Drechsler
Efficient Synthesis of Fault-Tolerant Controllers
R. Rochet, R. Leveugle, and G. Saucier
A Balanced Multilevel Decomposition Method
T. Luba and H. Selvaraj
A Precise Event-Driven Circuit Simulator Based On Predicted Fan-in Voltages
H. Fujisawa, F. Kawafuji, T. Kitaura, and T. Kage
Network Initialization in a Switch-Level Simulator
A.J. van Genderen
Direct Performance-Driven Placement of Mismatch-Sensitive Analogue Circuits
K. Lampaert, G. Gielen, and W. Sansen
SENSAT—A Practical tool for Estimation of the IC Layout Sensitivity to Spot Defects
W. Pleskacz and W. Kuzmicz
A Novel DFT Technique for Critical Bridging Faults in CMOS and BiCMOS ICs
M. Favalli, B. Ricco, and L. Penza
A Method for Testability Analysis and BIST Insertion at the RTL
J.E. Carletta and C.A. Papachristou
Thermal Test and Monitoring
V. Székely and M. Rencz
On Testability of Checkable Digital Circuits Under Pseudorandom Signals
A. Romankevich and V. Groll
Imperfect Linear Duplication of Combinational Circuits
R. Latypov and Y. Stolov
Test Preparation Methodology for High Coverage of Physical Defects in CMOS Digital Ics
M. Santos, I.C. Teixeira, J.P. Teixeira, and M. Simões
Fully Automatic DC Fault Dictionary Construction and Test Nodes Selection for Analogue Fault Diagnosis
J.S. Augusto and C.F.B. Almeida
A Comparative Study of Algorithms for A/D Converter Performance Evaluation by Statistical Analysis
D. Dallet, P. Marchegay, G. Franco, and C. Morandi
A Histogram Method for Analogue-Digital Converters Testing in Time and Spectral Domain
V.Y. Zagursky, N.Y. Semyonova, and M.V. Sirovatkin