Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, and C.-W. Albert Tsao,
"Bounded-Skew Clock and Steiner Routing,"
to appear in
ACM Trans. on Design Automation of Electronic Systems, 4(1), January, 1999.
Jason Cong and Cheng-Kok Koh,
"Interconnect Layout Optimization Under Higher-Order RLC Model,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design,
November, 1997, pp. 713-720.
Jason Cong, Lei He, Cheng-Kok Koh, and Zhigang Pan,
"Global Interconnect Sizing and Spacing with Consideration of Coupling
Capacitance,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design,
November, 1997, pp. 628-633.
Jason Cong, Lei He, Kei-Yong Khoo, Cheng-Kok Koh, and Zhigang Pan,
"Interconnect Design for Deep Submicron ICs,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design (Embedded Tutorial),
November, 1997, pp. 478-485.
Jason Cong, Lei He, and Cheng-Kok Koh,
Layout Optimization,
Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet,
NATO ASI Series, Kluwer Academic Publishers, 1997.
Jason Cong, Lei He, Cheng-Kok Koh, and Patrick H. Madden,
"Performance Optimization of VLSI Interconnect Layout,"
Integration, the VLSI Journal (Invited), Vol. 21, Nos. 1&2, November 1996, pp. 1-94.
K.-Y. Khoo, C.-K. Koh, J. Cong, and A. N. Willson, Jr.,
``Post-Layout Wire Optimization for
Performance and Reliability,''
in Mentor Graphics Users' Group 13th Annual International
Conference, October 1996.
J. Cong, C.-K. Koh and K.-S. Leung, ``Simultaneous Buffer and Wire Sizing for
Performance and Power Optimization,'' Proc. 1996
International Symposium on Low Power Electronics and Design, August 1996,
pp. 271--276.
J. Cong, A. B. Kahng, C.-K. Koh, and A. C.-W. Tsao,
"Bounded-Skew Clock and Steiner Routing Under Elmore Delay,"
Proc. ACM/IEEE International Conference on CAD-95, November 1995, pp. 66--71.
J. Cong and C.-K. Koh, ``Minimum-Cost Bounded-Skew Clock Routing,''
in IEEE International Symposium on Circuits and Systems,
April 1995, vol. 1, pp. 215--218.
J. Cong and C.-K. Koh, ``Simultaneous Driver and Wire Sizing for
Performance and Power Optimization,''
IEEE Transaction on VLSI Systems (Special Issue on Low-Power Design),
Dec 1994, Vol. 2, No. 4, pp. 408-425.
J. Cong and C.-K. Koh, ``Simultaneous Driver and Wire Sizing for
Performance and Power Optimization,''
Proc. IEEE International Conference on Computer-Aided Design,
Nov 1994, pp. 206--212.
J. Cong, C.-K. Koh and K.-S. Leung, ``Wiresizing with Driver Sizing
for Performance and Power Optimization'', Proc. 1994 International
Workshop on Low Power Design, 1994, pp. 81--86.