September 1993 to present: University of California, Los Angeles
Currently enrolled as a PhD student at the Department of Computer Science, with research interest on VLSI physical design problems, including interconnect design and clock routing.
June 1992 to May 1996: National University of Singapore
Master of Science.
Master Thesis: "Steiner Problem in the Octilinear Routing Model". Submitted in August 1995. Revised and accepted in May 1996.
July 1991 to April 1992: National University of Singapore
Bachelor of Science (Computer Science) with First Class Honors.
July 1988 to April 1991: National University of Singapore
Bachelor of Science (Computer Science).
June 1995 to September 1995: Silicon Valley Research, Mountain View
Employed as a summer intern, integrated wiresizing package developed at UCLA to optimize the performance of clock trees synthesized by the GARDS system.
September 1993 to present: University of California, Los Angeles
Employed as a research assistant with Dr. Jason Cong, developing interconnect design algorithms and working on clock routing problems.
May 1994 to present: UCLA VLSI CAD Lab
``Volunteered'' as system administrator of the VLSI CAD Lab, providing technical assistance to maintain Sun and HP and Linux workstations.
April 1994 to present: SIGDA University Booth
Involved in the SIGDA University Booth, setting up Unix Workstations at the DAC SIGDA University Booth to facilitate demonstrations of University research.
March 1994 to present: ACM SIGDA
Involved in the SIGDA Publications on CD-ROM project, providing technical assistance to put electronic versions of the proceedings of major design automation conferences and symposia for CAD (including ACM/IEEE Design Automation Conference, ACM/IEEE International Conference on CAD, European Design Automation Conference, European Design Automation Conference and Asia-South-Pacific Design Automation Conference) on CD-ROM.
May 1992 to September 1993: National University of Singapore
Employed as a teaching assistant at the Department of Information Systems and Computer Science. Job responsibilities included conducting tutorial classes and laboratory sessions for a Telecommunication and Networking course.
May 1991 to May 1992: Institute of Systems Science
Employed as a software engineer, developed an authoring tool to create hypertext documents automatically.
April 1990 to January 1991: Institute of Systems Science
Employed as an intern, developed a context-based information retrieval technique.
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, and C.-W. Albert Tsao,
"Bounded-Skew Clock and Steiner Routing,"
to appear in
ACM Trans. on Design Automation of Electronic Systems, 4(1), January, 1999.
Jason Cong and Cheng-Kok Koh,
"Interconnect Layout Optimization Under Higher-Order RLC Model,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design,
November, 1997, pp. 713-720.
Jason Cong, Lei He, Cheng-Kok Koh, and Zhigang Pan,
"Global Interconnect Sizing and Spacing with Consideration of Coupling
Capacitance,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design,
November, 1997, pp. 628-633.
Jason Cong, Lei He, Kei-Yong Khoo, Cheng-Kok Koh, and Zhigang Pan,
"Interconnect Design for Deep Submicron ICs,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design (Embedded Tutorial),
November, 1997, pp. 478-485.
Jason Cong, Lei He, and Cheng-Kok Koh,
Layout Optimization,
Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet,
NATO ASI Series, Kluwer Academic Publishers, 1997.
Jason Cong, Lei He, Cheng-Kok Koh, and Patrick H. Madden,
"Performance Optimization of VLSI Interconnect Layout,"
Integration, the VLSI Journal (Invited), Vol. 21, Nos. 1&2, November 1996, pp. 1-94.
K.-Y. Khoo, C.-K. Koh, J. Cong, and A. N. Willson, Jr.,
``Post-Layout Wire Optimization for
Performance and Reliability,''
in Mentor Graphics Users' Group 13th Annual International
Conference, October 1996.
J. Cong, C.-K. Koh and K.-S. Leung, ``Simultaneous Buffer and Wire Sizing for
Performance and Power Optimization,'' Proc. 1996
International Symposium on Low Power Electronics and Design, August 1996,
pp. 271--276.
J. Cong, A. B. Kahng, C.-K. Koh, and A. C.-W. Tsao,
"Bounded-Skew Clock and Steiner Routing Under Elmore Delay,"
Proc. ACM/IEEE International Conference on CAD-95, November 1995, pp. 66--71.
J. Cong and C.-K. Koh, ``Minimum-Cost Bounded-Skew Clock Routing,''
in IEEE International Symposium on Circuits and Systems,
April 1995, vol. 1, pp. 215--218.
J. Cong and C.-K. Koh, ``Simultaneous Driver and Wire Sizing for
Performance and Power Optimization,''
IEEE Transaction on VLSI Systems (Special Issue on Low-Power Design),
Dec 1994, Vol. 2, No. 4, pp. 408-425.
J. Cong and C.-K. Koh, ``Simultaneous Driver and Wire Sizing for
Performance and Power Optimization,''
Proc. IEEE International Conference on Computer-Aided Design,
Nov 1994, pp. 206--212.
J. Cong, C.-K. Koh and K.-S. Leung, ``Wiresizing with Driver Sizing
for Performance and Power Optimization'', Proc. 1994 International
Workshop on Low Power Design, 1994, pp. 81--86.
1996/97: Awarded the Chorafas Foundation Prize
1995/96: Awarded the GTE Fellowship
1993/94 to 1994/95: Awarded the Tan Kah Kee Foundation Postgraduate Scholarship
1989/90 to 1991/92: Awarded the National University of Singapore Scholarship
1989/90: Awarded the Lim Soo Peng Book Prize for Best Computer Science Student