Jason Cong, Lei He, and Cheng-Kok Koh,
Layout Optimization,
Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet,
NATO ASI Series, Kluwer Academic Publishers, 1997.
Cheng-Kok Koh's research interests include design and development of VLSI CAD algorithms and systems, design and analysis of data structures and algorithms, and design and development of automated authoring tools for hypertext and hypermedia systems.
At University of California, Los Angeles Computer Science Department, Cheng-Kok works with his advisor Dr. Jason Cong on interconnect layout optimization. They studied the simultaneous driver and wire sizing problem for performance and power optimization, and developed the first optimal driver and wire sizing algorithm. They also extended the result to consider buffer sizing simultaneously. Cheng-Kok also studied the problem of high-speed low-power clock design. In the bounded-skew clock routing problem, they considered trading clock skew for total wirelength; by allowing non-zero skew, the total wirelength can be significantly reduced. In the most recent work, they studied the performance-driven routing problem under a higher-order RLC model, with optimization of MCM interconnect being the main application.
Before entering UCLA, Cheng-Kok studied at National University of Singapore Department of Information Systems and Computer Science , where he worked with Dr. Hon-Wai Leong on the Steiner problem in the octilinear routing model. They derived the Steiner ratio for 3-point Steiner problem (approx. 0.854) and conjectured that this bound holds for the general n-point Steiner problem. They also generalized the Hanan's Theorem and showed that there exists an optimal octilinear Steiner tree with all Steiner points lying on the generalized Hanan's grid.
Cheng-Kok also worked with Dr. Tat-Seng Chua and Dr. Yin-Seong Ho of NUS on concept-based information retrieval technique and automatic hypertext authoring tool for hypertext and hypermedia system during his undergraduate study.
Jason Cong, Lei He, and Cheng-Kok Koh,
Layout Optimization,
Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet,
NATO ASI Series, Kluwer Academic Publishers, 1997.
Jason Cong and Cheng-Kok Koh, "Simultaneous Driver and
Wire Sizing for Performance and Power Optimization,"
IEEE Transaction on VLSI Systems (Special Issue on Low-Power Design),
December 1994, vol 2, no. 4, pp. 408-425.
Jason Cong, Lei He, Cheng-Kok Koh, and Patrick H. Madden,
"Performance Optimization of VLSI Interconnect Layout,"
Integration, the VLSI Journal (Invited), Vol. 21, Nos. 1&2, November 1996, pp. 1-94.
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, and C.-W. Albert Tsao,
"Bounded-Skew Clock and Steiner Routing,"
to appear in
ACM Trans. on Design Automation of Electronic Systems, 4(1), January, 1999.
Jason Cong, Cheng-Kok Koh, and Kwok-Shing Leung, "Wiresizing with
Driver Sizing for Performance and Power Optimization,"
Proc. 1994 International Workshop on Low Power Design, April 1994, pp. 81--86.
Jason Cong and Cheng-Kok Koh, "Simultaneous Driver and
Wire Sizing for Performance and Power Optimization,"
Proc.
ACM/IEEE International Conference on CAD-94, November 1994, pp. 206--212,
also in UCLA CSD Technical Report 940020, May 1994.
Jason Cong and Cheng-Kok Koh, "Minimum-Cost Bounded-Skew Clock Routing,"
Proc. 1995 International Symposium on Circuits and Systems, April 1995, vol. 1, pp. 215--218.
J. Cong, A. B. Kahng, C.-K. Koh, and A. C.-W. Tsao,
"Bounded-Skew Clock and Steiner Routing Under Elmore Delay,"
Proc. ACM/IEEE International Conference on CAD-95
, November 1995, pp. 66--71.
J. C
ong, C.-K. Koh and K.-S. Leung, ``Simultaneous Buffer and Wire Sizing for
Performance and Power Optimization,'' Proc. 1996
International Symposium on Low Power Electronics and Design, August 1996,
pp. 271--276.
K.-Y. Khoo, C.-K. Koh, J. Cong, and A. N. Willson, Jr.,
``Post-Layout Wire Optimization for
Performance and Reliability,''
Mentor Graphics Users' Group 13th Annual International
Conference, October 1996.
Jason Cong, Lei He, Kei-Yong Khoo, Cheng-Kok Koh, and Zhigang Pan,
"Interconnect Design for Deep Submicron ICs,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design (Embedded Tutorial),
November, 1997, pp. 478-485.
Jason Cong, Lei He, Cheng-Kok Koh, and Zhigang Pan,
"Global Interconnect Sizing and Spacing with Consideration of Coupling
Capacitance,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design,
November, 1997, pp. 628-633.
Jason Cong and Cheng-Kok Koh,
"Interconnect Layout Optimization Under Higher-Order RLC Model,"
Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design,
November, 1997, pp. 713-720.
Cheng-Kok Koh, "Steiner Problem in the Octilinear Routing Model,"
Master Thesis, National University of Singapore, submitted in August 1995,
revised and accepted in May 1996.