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Publications
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Architecture
and Compilation for Data Bandwidth Improvement in Configurable Embedded
Processors, (co-authored with J.Cong and Z. Zhang), Proceedings
of the 2005 IEEE/ACM International Conference on Computer Aided Design,
San Jose, CA, November 2005, pp. 263-270.[pdf]
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Instruction Set Extension with Shadow Registers for
Configurable Processors, (co-authored with J. Cong, Y. Fan, A. Jagannathan, G.
Reinman and Z. Zhang) to appear in Proceedings of the ACM International Symposium on
Field-Programmable Gate Arrays,
Feb. 2005. [pdf]
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Bitwidth-Aware Scheduling and Binding in High-Level Synthesis,
(co-authored with
J. Cong, Y. Fan,
Y. Lin, J. Xu, Z. Zhang and X. Cheng) Proceedings of
Asia
South Pacific
Design Automation Conference, Jan. 2005.[pdf]
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Architecture and Synthesis for On-Chip Multicycle Communication, (co-authored
with J. Cong, Y. Fan, X. Yang and Z. Zhang) IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems,
pp.550-564, Vol. 23, Apr. 2004. [pdf]
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Application-Specific Instruction Generation for
Configurable Processor Architectures, (co-authored with J. Cong, Y. Fan and Z. Zhang) Proceedings of
the ACM International Symposium on Field-Programmable Gate Arrays, pp.
183 - 189, February 2004.[pdf]
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Architectural Synthesis Integrated with Placement for Multi-Cycle
Communication, (co-authored with J. Cong, Y. Fan, X. Yang and Z.
Zhang) Proceedings
of the International Conference on Computer Aided Design, pp. 529-535, Nov. 2003. [pdf]
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Architecture and Synthesis for Multi-Cycle On-Chip Communication, (co-authored with J. Cong, Y. Fan, X. Yang and Z. Zhang) Proceedings of
First International Conference on Hardware/Software Codesign & System
Synthesis, pp. 77-78, 2003. [pdf]
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Contact Information
Office:
(310) 206-5449
Email:
leohgl@cs.ucla.edu
4651 Boelter Hall, Computer Science Department, UCLA, CA, 90095
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