Welcome to Chunyue Liu's Homepage
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I am a PhD candidate in
Center for Domain-Specific Computing &
VLSI CAD Lab in CS Department of UCLA. My advisor is
Prof. Jason Cong. My research
interests include power-efficient high-performance microprocessor
architecture design; architecture support for domain-specific computing;
architectural modeling and simulation of large-scale
systems.
• Ph.D. candidate, Computer Science Department, UCLA, since Fall 2007. • M.Sc. in major of Electronics Science & Technology, Zhejiang University, China, 2007. • B.Sc. in major of Electronics & Information Engineering, Zhejiang University, China, 2005. |
Research
My PhD research mainly focuses on power-efficient high-performance architecture design from three levels:
• Primary cache level: Adaptive Hybrid Cache: An energy-efficient adaptive fine-grained hybrid approach of cache and scratchpad memory
Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, and Yi Zou, "An Energy-Efficient Adaptive Hybrid Cache," In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 67-72, Fukuoka, Japan, August 2011. (Best Paper Award Nomination)
Jason Cong, Hui Huang, Chunyue Liu, and Yi Zou, "A Reuse-Aware Prefetching Algorithm for Scratchpad Memory, " In Proceedings of the 48th Annual Design Automation Conference (DAC), pp. 960-965, San Diego, CA, June 2011.
Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, and Yi Zou, "An Energy-Efficient Adaptive Hybridization of Cache and Scratchpad Memory for Customizable Computing Engines," In Proceedings of SRC TECHCON Conference, Austin, TX, September 2011.
• Shared cache level: Heterogeneity in terms of both architectural components (caches vs. accelerator buffers) and memory technologies (SRAM vs. non-volatile memories)
Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, and Glenn Reinman, "BiN: A Buffer-in-NUCA Scheme for Accelerator-Rich CMPs," To appear in International Symposium on Low Power Electronics and Design (ISLPED), Redondo Beach, CA, July 2012.
Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar, and Glenn Reinman, "Static and Dynamic Co-Optimizations for Blocks Mapping in Hybrid Caches," To appear in International Symposium on Low Power Electronics and Design (ISLPED), Redondo Beach, CA, July 2012.
Yu-Ting Chen, Jason Cong, Hui Huang,
Bin
Liu,
Chunyue Liu,
Miodrag Potkonjak, and Glenn Reinman, "Dynamically Reconfigurable Hybrid
Cache: An Energy-Efficient Last-Level Cache Design", To appear in
the
Proceedings of Design, Automation and Test in Europe (DATE),
Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman, and Yi Zou, "AXR-CMP: Architecture Support in Accelerator-Rich CMPs," In Proceedings of the 2nd Workshop on SoC Architecture, Accelerators and Workloads (SAW-2), San Antonio, TX, February 2011.
• On-chip interconnections level: High-performance and power-efficient NoC (Network-on-Chip) design
Jason Cong, Chunyue Liu, and Glenn Reinman, "ACES: Application-Specific Cycle Elimination and Splitting for Deadlock-Free Routing on Irregular Network-on-Chip, " In Proceedings of the 47th Design Automation Conference (DAC), pp. 443-448, Anaheim, CA, June 2010.
M. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, and Sai-Wang Tam, "Power Reduction of CMP Communication Networks via RF-Interconnects," In Proceedings of the 41st Annual International Symposium on Microarchitecture (MICRO), pp. 376-387, Lake Como, Italy, November 2008.
Jason Cong, Chunyue Liu, and Guojie Luo, "Quantitative Studies of Impact of 3D IC Design on Repeater Usage," In Proceedings of the 25th International VLSI/ULSI Multilevel Interconnection Conference (VMIC), pp. 344-348, Fremont, CA, October 2008. (Invited Paper)
• Evaluation of static analysis techniques for fixed-point precision optimization
Before going to UCLA, I was a research assistant in Institute of VLSI Design, Zhejiang University, where I participated in the design of an application-specific instruction set processor (ASIP): Media Processor.
Overview slides in the Workshop of International Center on Design for Nanotechnologies (ICDFN), August 2006.
Chunyue Liu, Xiaolang Yan, and Xing Qin. "An Optimized Linear Skewing Interleave Scheme for On-chip Multi-access Memory Systems," In Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 8-13, Stresa-Lago Maggiore, Italy, March 2007.
Chunyue Liu, Xing Qin, and Xiaolang Yan. "Explicit Data Organization SIMD Instruction Set Architecture for Media Processors," In Proceedings of the 25th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN), pp. 227-232, Innsbruck, Austria, February 2007.
Internship
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• 1/2011-6/2011 |
Google Inc., Seattle, WA |
Developed large scale system simulation infrastructure of Google cluster cells using MapReduce, in order to assess the quality and guide the development of estimation tools of cell contention and service schedulability |
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6/2010-9/2010
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IBM T. J. Watson Research Center, Yorktown Heights, NY |
| Reduced the power consumption of IBM wire-speed-processor by selectively re-designing the instruction unit micro-architecture, from cycle accurate C++ modeling to RTL implementation |
Courses Taken
• Fall 2007
EE236A (Linear Programming), CS251A (Advanced Computer Architecture)
• Winter 2008
EE236B (Nonlinear Programming), CS280G (Algorithms: Graphs and Networks)
• Spring 2008
CS259 (Lecture 1, Microprocessors Architecture), CS259 (Lecture 3, Embedded Systems: System Synthesis-Based Approach)
• Fall 2008
CS259 (System Design/Architecture)
• Winter 2009
CS252A (Arithmetic Algorithms and Processors), CS180 (Introduction to Algorithms and Complexity)
• Spring 2009
CS258F (Physical Design Automation of VLSI Systems), CS289RA (Randomized Algorithms)
Teaching
• Spring 2009
CS33 (Introduction to Computer Organization)
Contact
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Address: UCLA Computer Science Dept., 4420 Boelter Hall, Los Angeles, CA 90095
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