Jason Cong and Zhigang Pan, "Wire Width Planning and Performance Optimization for VLSI Interconnects, U.S. Patent No. 6,408,427

Jason Cong, Zhigang Pan, and P.V. Srinivas, "An Apparatus for Accurate and Efficient Calculation of Crosstalk Noise in Integrated Circuits". (U.S. patent pending)

Ruchir Puri, Zhigang Pan, Anthony Correale, Jr., David S. Kung, and Rajeev Joshi, "Logic Circuit for Power Efficient Voltage Level Converter", IBM Research Disclosure YOR820030155. (U.S. patent pending)

Zhigang Pan, Anthony Correale, Jr., David S. Kung, Douglas T. Lamb, Ruchir Puri, and David Wallach, "Method and Apparatus for Dual Voltage Designs with Generic Voltage Islands", IBM Research Disclosure YOR820030180. (U.S. patent pending)

Zhigang Pan, Anthony Correale, Jr., David S. Kung, and Ruchir Puri, "Methods of Processing Level Converters for Multiple Voltage Designs", IBM Research Disclosure YOR820030182. (U.S. patent pending)

L. Trevillyan et al, "A Method for Achieving Design Closure on Chip or Macro-level Electronic Designs", IBM Research Disclosure YOR820030229. (U.S. patent pending)

Interconnect Synthesis and Planning for High-Performance IC Designs, Ph.D. Thesis, University of California, Los Angeles, 2000.

" Multilevel Global Placement with Congestion Control", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp.395-409, April 2003. (with C.-C. Chang, J. Cong and X. Yuan).

" Wire Width Planning for Interconnect Performance Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp.319-329, March 2002. (with J. Cong).

" Buffer Block Planning for Interconnect Planning and Prediction", IEEE Transactions on VLSI Systems , vol. 9, no. 6, pp.929-937, December 2001. (with J. Cong and T. Kong).

" Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1164-1169, September 2001. (with J. Cong, L. He and C.-K. Koh).

" Interconnect Performance Estimation Models for Design Planning" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001 (with J. Cong).

" Pushing ASIC Performance in a Power Envelope", Proc. 40th ACM/IEEE Design Automation Conference (DAC), Anaheim, California, June, 2003. (with L. Stok, R. Puri, J. Cohn, D. Kung, D. Sylvester, A. Srivastava, and S. H. Kulkarni).

"Generic Voltage Island: CAD Flow and Design Experience", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003. (with A. Correale, D. Lamb, D. Wallach, D. Kung, and R. Puri).

"A Flexible Design Approach for the Use of Dual Supply Voltages and Level Conversion for Low-Power ASIC Design", Austin Conference on Energy Efficient Design (ACEED), Austin, Texas, Feb, 2003. (with R. Puri and D. Kung).

" Physical Hierarchy Generation with Routing Congestion and Control", Proc. International Symposium on Physical Design (ISPD), pp36-41, San Diego, California, April 2002. (with C.-C. Chang, J. Cong and X. Yuan).

" Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan (with J. Cong and P.V. Srinivas).

" Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Proc. ACM/ACM TAU, Dec. 4-5, 2000, Austin, (with J. Cong and P.V. Srinivas).

" Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization", Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix, (with C.-C. Chang, J. Cong, and X. Yuan).

" Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization", Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix, (with J. Cong and P.V. Srinivas).

" Buffer Block Planning for Interconnect-Driven Floorplanning", Proc. ACM/IEEE Int'l Conference on Computer-Aided Design (ICCAD) , November, 1999. (with J. Cong, and T. Kong) The presentation slides are also available.

" Interconnect Estimation and Planning for Deep Submicron Designs", Proc. ACM/IEEE 36th Design Automation Conference (DAC) , June 20-5, 1999, New Orleans. (with J. Cong) The presentation slides are also available.

" Interconnect Delay and Area Estimation for Multiple-Pin Nets", Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 8-9, 1999, Monterey. (with J. Cong). The presentation slides are also available.

" Interconnect Delay Estimation Models for Synthesis and Design Planning", Proc. Asian and South Pacific Design Automation Conference (ASPDAC), January 18-21, 1999, Hong Kong (with J. Cong). The presentation slides are also available.

" Interconnect Delay Estimation Models for Logic and High Level Synthesis", Proc. SRC Techcon Conference, September 9-11, 1998, Las Vegas. (with J. Cong).

" Interconnect Performance Estimation Models for Synthesis and Design Planning", ACM/IEEE Int'l Workshop on Logic Synthesis, June, 1998. (with J. Cong).

" Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", Proc. ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November, 1997. (with J. Cong, L. He and C.-K. Koh.)

" Interconnect Design for Deep Submicron ICs", Proc. ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November, 1997. (with J. Cong, L. He, K.-Y. Khoo, and C.-K. Koh).

"Interannual and Subannual variability of the wind-driven, double-gyre circulations", American Geophysical Union Fall Meeting , 1996 (with K. Ide and M. Ghil)

"Interannual and Subannual variability of wind-driven ocean gyre circulations", First Annual Meeting, Modeling and Prediction of Water Resources in California and the Western United States , 1996 (with K. Ide and M. Ghil)

" Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", UCLA Technical Report, CSD-200011, 2000. (with J. Cong, L. He and C.-K. Koh).

" Buffer Block Planning for Interconnect-Driven Floorplanning", UCLA Technical Report, CSD-990036, 1999. (with J. Cong and T. Kong)

" Interconnect Estimation and Planning for Deep Submicron Designs", UCLA Technical Report, CSD-980035, 1998. (with J. Cong)

" Interconnect Performance Estimation Models for Synthesis and Design Planning", UCLA Technical Report, CSD-980017, 1998. (with J. Cong)

" Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", UCLA Technical Report, CSD-970031, 1997. (with J. Cong, L. He and C.-K. Koh).

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