TRIO release B 1.0

Technical References

Project Director:    Prof. Jason Cong
Copyright© 1993-1999 the Regents of University of California

The following are publications concerning TRIO algorithms. All except [9] and [11] were developed in UCLA CAD group.

  1. J. Cong and L. He, "Optimal Wiresizing for Interconnects with Multiple Sources," ACM Trans. on Design Automation of Electronic Systems, 1(4),pp. 478-511, October 1996.
  2. J. Cong and L. He, "An Efficient Approach to Simultaneous Transistor and Interconnect Sizing", ACM/IEEE Int'l Conf. on Computer- Aided Design, Dec.,1996, pp. 181-186.
  3. J. Cong and L. He, "Theory and Algorithm of Local Refinement Based Optimization with Application to Device and Interconnect Sizing", IEEE Trans. on Computer-Aided Design, April 1999, pp. 1--14.
  4. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", ACM/IEEE Design Automation Conference, 1997, pp. 627-632.
  5. J. Cong, L. He, C.K. Koh and Z. Pan, "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", ACM/IEEE Int'l Conf. on Computer-Aided Design, Dec. 1997, pp. 628-633.
  6. J. Cong and C.-K. Koh, "Simultaneous Driver and Wire Sizing for Performance and Power Optimization," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2(4), December 1994, pp. 408-423.
  7. J. Cong, C.-K. Koh, and K.-S. Leung, "Simultaneous Buffer and Wire Sizing for Performance and Power Optimization," Proc. Int'l Symp. on Low Power Electronics and Design, August 1996, pp. 271--276.
  8. J. Cong and K. S. Leung, "Optimal wiresizing under the distributed Elmore delay model," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, pp. 321--336, Mar. 1995.
  9. J. Lillis, C. K. Cheng, and T. T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," in Proc. Int. Conf. on Computer Aided Design, pp. 138--143, Nov. 1995.
  10. T. Okamoto and J. Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," in Proc. Int. Conf. on Computer Aided Design, pp. 44--49, Nov. 1996.
  11. L. P. P. Van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay," in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 865--868.
  12. Slide show for TRIO.