Wei  Jiang

Education
    1995-1999     Peking University, China (BS Received)
    1999-2002     Peking University, China (MS Received)
    2003-2004     University of Rochester (Ph.D student)
    2004-2009     UCLA (Ph.D Received)

Research
    My research interests include compilers and behavioral synthesis.

Software Release
    The approximate pattern recognition library: APR.

Publications
  1. J. Cong, H. Huang, and W. Jiang, "A Generalized Control-Flow-Aware Pattern Recognition Algorithm for Behavior Synthesis", Proceedings of Design, Automation and Test Europe (DATE 2010), Dresden, Germany, March 2010.
  2. J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou, "Accelerating Monte-Carlo based SSTA using FPGA", Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, CA, February 2010.
  3. J. Cong, W. Jiang, B. Liu, and Y. Zou, "Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization", Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 697-704, November 2009.
  4. J. Cong, K. Gururaj, G. Han, and W. Jiang,"Synthesis Algorithm for Application-Specific Homogeneous Processor Networks," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 9, pp.1318-1329, September 2009.
  5. Z. Zhang, Y. Fan, W. Jiang, G. Han, C. Yang, and J. Cong, "AutoPilot: A Platform-Based ESL Synthesis System," "High-Level Synthesis: From Algorithm to Digital Circuit," ed. P. Coussy and A. Morawiec, Springer Publishers, 2008.
  6. J. cong, W. Jiang, "Pattern-based Behavior Synthesis for FPGA Resource Reduction", Proceedings of the 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2008.
  7. J. Cong, W. Jiang, M. Potkonjak and Z. Zhang, "Scheduling with Integer Delay Budgeting for Low-Power Optimization", Proceedings of ASP DAC, January 2008.
  8. J. Cong, G. Han, and W. Jiang, "Synthesis of an Application-Specific Soft Multiprocessor System ," Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2007.
  9. J. Cong, Y. Fan, and W. Jiang, "Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture," Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2006.
  10. J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "Platform-Based Behavior-Level and System-Level Synthesis (Invited Paper)," Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006.
  11. J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang, "Behavior and Communication Co-Optimization for Systems with Sequential Communication Media," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.
  12. Memory Access Analysis and Optimization Approaches on Splay Trees. LCR 2004,Seventh Workshop on Languages, Compilers, and Run-time Support for Scalable Systems. Wei Jiang, Chen Ding, and Roland Cheng.
  13. The Parallel Application Template Based on Extrinsic Supported in p-HPF. Computer Engineering and Applications, Page 30-34, Vol.37, 2001. Changjun Hu, Wei Jiang, Aisheng Lu, Huashan Yu, Zhuoqun Xu.
  14. Compiling Methods Supporting Multi-Paradigm Parallel Computing in p-HPF. Chinese J.Computers, Vol24, No.7, July 2001. Changjun Hu, Wei Jiang, Aisheng Lu, Zhuoqun Xu.

Contact me:
4651 Boelter Hall, UCLA 
Los Angeles,CA 90095 
wjiang@cs.ucla.edu
Tel: 310-206-5449