Acceleration of Logic Synthesis Algorithms using FPGA-based Reconfigurable Coprocessors

In this project, we implemented two fundamental logic synthesis algorithms, tautology checking and binate covering, using an FPGA-based reconfigurable application-specific coprocessor. We compare our hardware accelerator for the tautology check algorithm with the software implementation of the tautology check algorithm in Espresso II [RuVi87]. Our experimental results show that our accelerator is capable of achieving a maximum speedup factor of 2.94 and averaging 1.36 on 110 modified industry benchmarks included with the Espresso II package.

Cong, J., J. Peck, "On Acceleration of Logic Synthesis Algorithms using FPGA-based Reconfigurable Coprocessors", UCLA Technical Report TR-970010.