Technology Mapping for FPGAs with Embedded Memory Blocks

Modern field programmable gate arrays (FPGAs) provide embedded memory blocks (EMBs) to be used as on-chip memories. We explored the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. We propose a general technology mapping problem for FPGAs with EMBs for area and delay minimization and develop an efficient algorithm based on the concepts of Maximum Fanout Free Cone (MFFC) and Maximum Fanout Free Subgraph (MFFS), named EMB_Pack, which minimizes the area after or before technology mapping by using EMBs while maintaining the circuit delay.

We have tested EMB_Pack on MCNC benchmarks on Altera's FLEX10K device family. The experimental results show that compared with the original mapped circuits generated from CutMap without using EMBs, EMB_Pack as postprocessing can further reduce up to 10% of the area on the mapped circuits while maintaining the layout delay by making efficient use of available EMB resources. Compared with CutMap-e without using EMBs, EMB_Pack as pre-mapping processing followed by CutMap-e can reduce 6% of the area while maintaining the circuit optimal delay.

Benchmarks for EMB_Pack as postprocessing: Fifteen MCNC Benchmarks after CutMap

Cong, J., S. Xu "Technology Matching for FPGAs with Embedded Memory Blocks" Proc. ACM International Symposium on FPGA, Monterey, CA., Feb. 1998, pp. 179-188.