Young-kyu Choi

ykchoi@cs.ucla.edu

Research Interest

Automated performance analysis and debugging for HLS-based FPGA designs

Characterization of FPGA-friendly applications with FPGA-GPU platform comparison

Acceleration of various applications using FPGA

 

Education

Ph.D. student in Computer Science

University of California, Los Angeles

(Advisor: Prof. Jason Cong)

M.S. degree in Electrical Engineering and Computer Science

Seoul National University, Seoul, Korea

(Advisor: Prof. Wonyong Sung)

B.S. degree in Electrical Engineering

Seoul National University, Seoul, Korea

 

Sept. 2012 ~ Present

 

 

Mar. 2006 ~ Feb. 2008

 

 

Mar. 2002 ~ Feb. 2006

 

 

Publications

 

Journal

[1] Young-kyu Choi and J. Cong, "Acceleration of EM-based 3D CT reconstruction using FPGA," IEEE Trans. Biomedical Circuits and Systems (TBCAS), vol. 10, no. 3, pp. 754-767, Jun. 2016.

[2] I. Park, M. Lee, and Young-kyu Choi, "Survey of computer vision technologies on embedded platform," Journal of Institute of Electronics Engineers of Korea (IEEK), vol. 39, no. 2, pp. 85-92, Feb. 2012. (Invited, in Korean)

[3] K. You, Young-kyu Choi, J. Choi, and W. Sung, "Memory access optimized VLSI for 5,000-word continuous speech recognition," Journal of Signal Processing Systems (JSPS), vol. 63, no. 1, pp. 95-105, Apr. 2011.

[4] Young-kyu Choi, K. You, J. Choi, and W. Sung, "A real-time FPGA-based 20,000-word speech recognizer with optimized DRAM access," IEEE Trans. Circuit and Systems (TCAS) I: Regular Papers, vol. 57, no. 8, pp. 2119-2131, Aug. 2010.

 

Conference

[5] Young-kyu Choi, P. Zhang, P. Li, and J. Cong, "HLScope+: Fast and accurate performance estimation for FPGA HLS," in Proc. IEEE/ACM Int. Conf. Computer Aided Design (ICCAD), Irvine, pp. - , Nov. 2017.

[6] Young-kyu Choi and J. Cong, "HLScope: High-level performance debugging for FPGA designs," in Proc. IEEE Int. Symp. Field-Programmable Custom Computing Machines (FCCM), Napa, pp. 125-128, May 2017.

[7] Young-kyu Choi, J. Cong, Z. Fang, Y. Hao, G. Reinman, and P. Wei, "A quantitative analysis on microarchitectures of modern CPU-FPGA platforms," in Proc. Design Automation Conference (DAC), Austin, pp. 109-114, Jun. 2016.

[8] Young-kyu Choi, J. Cong, and D. Wu, "FPGA implementation of EM algorithm for 3D CT reconstruction," in Proc. IEEE Int. Symp. Field-Programmable Custom Computing Machines (FCCM), Boston, pp. 157-160, May 2014.

[9] Young-kyu Choi and I. Park, "GPU acceleration of graph cuts for stereo matching," Embedded Vision Workshop (EVW), Portland, pp. 642-648, Jun 2013.

[10] Young-kyu Choi, Williem, and I. Park, "Memory-efficient belief propagation in stereo matching on GPU," Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA), Los Angeles, pp. 1-4, Dec. 2012.

[11] Young-kyu Choi, "CUDA implementation of belief propagation for stereo vision," in Proc. IEEE Int. Conf. Intelligent Transportation Systems (ITSC), Madeira, pp.1402-1407, Sept. 2010.

[12] Young-kyu Choi, K. You, J. Choi, and W. Sung, "VLSI for 5,000-word continuous speech recognition," in Proc. IEEE Intl. Conf. Acoustics, Speech and Signal Processing (ICASSP), Taipei, pp.557-560, Apr. 2009.

[13] Young-kyu Choi, K. You, and W. Sung, "FPGA-based implementation of a real-time 5000-word continuous speech recognizer," in Proc. European Signal Processing Conference (EUSIPCO), Lausanne, Aug. 2008.

 

Research / Academic Experience

 

UCLA (Set 2012 ~ present)

l  Performance analysis and debugging in FPGA system [5, 6, 7]

l  Acceleration of medical image processing on Convey platform [1, 8]

l  Advisor: Prof. Jason Cong

 

Inha University (Nov 2011 ~ Aug 2012)

l  GPGPU implementation of large-scaled MRF for stereo matching using graph cuts / belief propagation [2, 9, 10, 11]

l  Advisor: Prof. In Kyu Park

 

Seoul National University (Mar 2006 ~ Feb 2008)

l  FPGA/VLSI implementation of large vocabulary continuous speech recognizer [3, 4, 12, 13]

l  Advisor: Prof. Wonyong Sung

 

Invited Talks

l  "CUDA-based parallelization of optimization problems for computer vision applications," NVIDIA CUDA Workshop Korea 2012, Seoul, July 2012.

 

Academic Activities

l  Reviewer for FPGA, FCCM, FPL, TC, TNNLS, ICPR, SP

 

Teaching Experience

l  Lecturer, "Object-oriented Programming I" at Inha University (Spring 2012)

l  TA, " Introductory Digital Design Laboratory" at UCLA (Winter, Spring 2017)

l  TA, "Parallel and Distributed Computing" at UCLA (Winter 2015)

l  TA, "Logic Design of Digital Systems" at UCLA (Spring 2014)

l  TA, "Introduction to Computer Science I" at UCLA (Winter 2014)

l  TA, "Design Project for Electrical Devices & Systems" at SNU (Spring 2007)

l  TA, "Computer Organization" at SNU (Fall 2006)

 

Work Experience

 

LG Electronics (Mar 2008 ~ Oct 2011)

l  Position: Research Engineer at System IC team

l  Expertise: Digital circuit designer for communication chip

l  Major projects:

n  OFDM-based synchronizer design for Chinese mobile TV (CMMB) (Oct 2008 ~ Dec 2009)

n  Analog TV (NTSC, PAL, SECAM) demodulator design (Oct 2010 ~ Oct 2011)

 

Falcon Computing Solutions (Jul 2017 ~ Sept 2017)

l  Project:

n  FPGA performance estimator for Merlin Compiler

 

Others

l  Developed English pronunciation games (Toby) using Nintendo DS (Jan 2006 ~ Mar 2006)

l  Intern at Samsung Electronics (LSI division - chip quality test) (July 2004, Dec 2004)

 

 

 

Last updated: Sept. 2017.