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I am a fifth year PhD student in Computer Science Department, UCLA. I work in VLSI CAD Lab headed by Prof. Jason Cong. My research interests focus on physical design for VLSI system, especially on interconnect planning and optimization, placement, global routing in deep submicron design.  I also enjoy working in the fields other than physical design, such as technology mapping for FPGA.

Education

9/1998 - present
Ph.D. student in Computer Science Department, University of California, Los Angeles.
Advisor: Prof. Jason Cong
Research work: Physical design for VLSI, interconnect-driven physical planning, placement, global routing, technology mapping for FPGA.
9/1996-7/1998
Master of Engineering in Computer Application, Department of Computer Science and Technology, Tsinghua University, Beijing, P. R. China.
Research work: Physical design for VLSI, detailed placement and channel routing.
9/1991-7/1996
Bachelor of Engineering in Computer Science and Technology, Department of Computer Science and Technology, Tsinghua University, Beijing, P. R. China.

Research Publications

  1. "Multilevel Global Placement with Retiming," (co-authored with J. Cong), Proc. ACM/IEEE 40th Design Automation Conference, Anaheim, CA., June 2003, pp. 208-213.
  2. "Multilevel Global Placement with Congestion Control", (co-authored with C.-C.Chang, J. Cong and Z. Pan,) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 22, no. 4, pp. 395-409, April 2003
  3. "Multi-level Placement for Large-Scale Mixed-Size IC Designs", (co-authored with C.-C. Chang and J. Cong,) Proc. Asia South Pacific Design Automation Conference, pp 325-330, January 2003.
  4. "Physical Hierarchy Generation with Routing Congestion and Control", (co-authored with C.-C.Chang, J. Cong and Z. Pan,) Proc. International Symposium on Physical Design, pp36-41, San Diego, California, April 2002.
  5. " Power Model for Interconnect Planning,"  (co-authored with C.-C. Chang, J. Cong and T. Uchino,) Procedings of the Workshop on Synthesis And System Integration of Mixed Technologies, pp. 234 - 241, October 2001.
  6. " Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization", (co-authored with C.-C. Chang, J. Cong, and D. Pan), Proc. SRC Techcon Conference, September 21-3, 2000, Phoenix, AZ.
  7. " Routing Tree Construction Under Fixed Buffer Locations " (co-authored with J. Cong), Proc. ACM/IEEE 37th Design Automation Conference, Los Angeles, CA., June 2000, pp. 379-384.
  8. " Technology Mapping for k/m-macrocell Based FPGAs" (co-authored with J. Cong and H. Huang), Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, CA., Feb. 2000, pp. 51-59.
  9. " Detailed Placement for Standard Cell", the 10th Chinese CAD & CG Conference, Oct. 8-11, 1998, Guiling, China. (in Chinese)
  10. " A Three-layer Channel Routing Algorithm Appropriate to Gate Array and Standard Cell", Microelectronics and Computer, Sept. 1998. (in Chinese)

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