Welcome to the home page of Yi Zou

 

I am a sixth-year graduate student in VLSICAD Lab in CS Dept of UCLA, my advisor is Jason Cong.

 

Curriculum Vitae

 

Research Interests:

  • Acceleration of Domain Specific Computation
  • Scientific computing and optimization
  • Statistical and variational modeling and simulation
  • VLSI Physical design

 

 

Education

  • Ph.D. student, Computer Science Department, UCLA, since Fall 2006.
  • M.E. in Computer Science, Tsinghua University, Beijing, China, 2006.
  • B.E. in Computer Science, Tsinghua University, Beijing, China, 2004.

 

Courses Taken

  • Fall 2006 

EE216A(Design of VLSI Circuits and Systems)   EE236A(Linear Programming)

  • Spring 2007

EE209S2(Special Topics in Embedded Computing Systems )  EE236B(Nonlinear Programming)

  • Fall 2007

CS239(Parallel programming languages)  CS251A(Advanced Computer Architecture)

  • Winter 2008

CS259(Special topics on Embedded Systems (on security))  CS252A(Arithmetic Algorithms and Processors)

  • Spring 2008

CS259(Special topics on Embedded Systems (on system-level approaches))  CS259 (topics on Embedded Systems (on wireless health))

  • Spring 2009

CS258F(VLSI physical design automation) 

 

 

 

Teaching

  • Spring 2010 

CS133(Parallel and Distributed Computing)   

Contact

ZOU, YI

Research Assistant, VLSI CAD Lab

UCLA Computer Science Department

4651 Boelter Hall

Los Angeles, CA 90095

Tel: (310) 689-9644

Email: zouyi@cs.ucla.edu

 

 

Publications:

(Note: papers from Prof Cong's group are listed in alphabetic order, bolded papers are those I am the corresponding author)

 

Journals or Magazines

 

J1.              Y. Zou, Y. Cai , Q. Zhou , X. Hong, S. X. -D. Tan, "A Fast Delay Computation for The Hybrid Structured Clock Network",  IEICE Trans on Fundamentals of Electronics  Communications and Computer Sciences E SERIES A, Vol. 88, No.7, 2005

J2.               Y. Wang, Y. Cai , X. Hong, Y.Zou, " Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration",  IEICE Trans on Fundamentals of Electronics  Communications and Computer Sciences E SERIES A, Vol. 90, No.5, 2007

J3.              J. Cong and Y. Zou, FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation, ACM Transactions on Reconfigurable Technology and Systems, Vol.2, No.3, Article 17, 2009

J4.               J. Cong, W. Jiang, B. Liu and Y. Zou, Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization, ACM Transactions on Design Automation of Electronic Systems, Volume 16, Number 2, Article 15, March 2011.

J5.               Y. Hu, Y-T Wang, A.Stoelting, Y. Zou and M. Sarrafzadeh, Providing a cushion for wireless healthcare application development, IEEE Potentials Magazine, Vol 29, No. 1, 2010.

 

Conferences and Workshops

 

C1.             Y. Zou, Y. Cai , Q. Zhou , X. Hong, S. X. -D. Tan, "A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network",  Proc. of the IEEE International Conference on Computer Design (ICCD'04), pp.344-349,  2004

C2.              Y. Zou, Y. Cai , Q. Zhou , X. Hong, S. X. -D. Tan, "Analysis of Buffered Hybrid Structured Clock Networks",  Proc. of the 2005 conference on Asia South Pacific design automation,(ASPDAC'05), pp.93-98, 2005 

C3.             Y. Zou, M. Zhang, Y. Cai, Q. Zhou, X. Hong, Minimum Error Based Affine Arithmetic for Variational Timing Analysis, Proc. 6th International Conference On ASIC, (ASICON05), pp 978-981,2005.

C4.             Y. Zou, Y. Cai , Q. Zhou , X. Hong, S. X. -D. Tan , Worst-case Clock Delay Simulation under PG Variation Using Gradient Projection Method, Proc. of International Conference on Communications, Circuits and Systems Proceedings (ICCCAS05), 2005

C5.             Y. Zou, Y. Cai , Q. Zhou , X. Hong, S. X. -D. Tan ,Interval Valued Variational Analysis Using the Arithmetic of Higher Order Polynomial, Proc. of International Conference on Communications, Circuits and Systems Proceedings (ICCCAS06), pp 2444-2448, 2006

C6.             Q. Zhou ,Y. Zou, Y. Cai, X. Hong, Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS06), pp 1635-1638, 2006

C7.             Y. Zou, Y. Cai , Q. Zhou , X. Hong, S. X. -D. Tan, L. Kang, "Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos", Proceedings of the 2007 conference on Asia South Pacific design automation(ASPDAC'07),pp.367-372, 2007 

C8.             L. Kang, Y. Cai, Y. Zou, J. Shi, X. Hong, S. X.-D. Tan, "Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach", Proc. of the 2007 conference on Asia South Pacific design automation(ASPDAC'07), pp.751-756, 2007 

C9.             J. Cong and Y. Zou, Lithographic Aerial Image Simulation with FPGA-Based Hardware Acceleration, in Proc. International Symposium on Field-Programmable Gate Arrays(FPGA08), pages 20-29, Monterey CA, Feb 2008

C10.         J. Cong, K. Gururaj, B. Liu, C. Liu, Z. Zhang, S. Zhou and Y. Zou, "Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization", in Proc. International Symposium on Field-Programmable Custom Computing Machines(FCCM), pages 231-234, Napa CA, Apr 2009

C11.         J. Cong and Y. Zou, Parallel Multi-level Analytical Global Placement on Graphics Processing Units, in Proc. International Conference on Computer-Aided Design(ICCAD), pages 681-688, San Jose CA, Nov 2009

C12.         J. Cong, W. Jiang, B. Liu, and Y. Zou, Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization, in Proc. International Conference on Computer-Aided Design(ICCAD), pages. 697-704, San Jose, CA, Nov 2009.

C13.         J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou, Accelerating Monte-Carlo based SSTA using FPGA, in Proc. International Symposium on Field-Programmable Gate Arrays(FPGA), pages 111-114, Monterey, CA, Feb 2010.

C14.         J. Cong and Y. Zou, A Comparative Study on the Architecture Templates for Dynamic Nested Loops, in Proc. International Symposium on Field-Programmable Custom Computing Machines(FCCM), pages 251-254, Charlotte, NC, May 2010

C15.         J. Cong, M. A. Ghodrat, M. Gill, C. Liu, G. Reinman and Y. Zou, AXR-CMP: Architecture Support in Accelerator-Rich CMPs, in Proc. Workshop on SoC Architecture, Accelerators and Workloads(SAW), San Antonio, TX, Feb 2011.

C16.         J. Cong, H. Huang, C. Liu and Y. Zou, A Reuse-Aware Prefetching Algorithm for Scratchpad Memory, Proc. Design Automation Conference(DAC), San Diego, CA, Jun 2011.

C17.         J. Cong, M. Huang and Y. Zou, 3D Recursive Gaussian IIR on GPU and FPGAs, Proc. IEEE Symposium on Application Specific Processors(SASP), San Diego, CA, Jun 2011.

C18.         J. Cong, K. Gururaj, H. Huang, C. Liu, G. Reinman and Yi Zou, An Energy-Efficient Adaptive Hybrid Cache, Proc. International Symposium on Low Power Electronics and Design(ISLPED), Fukuoka, Japan, Aug 2011. (Best Paper Nomination)

C19.          J. Cong, M. Huang and Y. Zou, Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms, Proc. International Conference on Field Programmable Logic and Applications(FPL), Chania, Crete, Greece, Sep 2011

C20.         J. Cong, K. Gururaj, M. Huang, S. Li, B. Xiao and Y. Zou, "Domain-Specific Processor with 3D Integration for Medical Image Processing", Proc. IEEE International Conference on. Application-specific Systems, Architectures and Processors (ASAP)Santa MonicaCA, pp. 247-250, September 2011.

C21.         J. Cong, M. Huang  B.Liu , P.Zhang and Y. Zou, Combining Module Selection and Replication for Throughput-Driven Streaming Programs, Proc. Design, Automation, and Test in Europe, 2011

C22.          J. Cong, P. Zhang and Y. Zou, Combined Loop Transformation and Hierarchy Allocation for Data Reuse Optimization, Proc. International Conference on Computer-Aided Design(ICCAD) , San Jose CA, Nov 2011

C23.          A. Bui, K. Cheng, J. Cong, L. Vese, Y. Wang, B. Yuan and Y. Zou, "Platform Characterization for Domain-Specific Computing (invited paper) ", Proc. Conference on Asia South Pacific Design Automation(ASPDAC), Sydney, Australia, Jan 2012

C24.          J. Chen, J. Cong, M. Yan and Y. Zou, " FPGA-Accelerated 3D Reconstruction using Compressive Sensing", Proc. International Symposium on Field-Programmable Gate Arrays(FPGA), Monterey CA, Feb 2012

C25.         A. Sbirlea, Y. Zou, Z. Budimlic, J. Cong and V. Sarkar, Mapping a Data-Flow Programming Model onto Heterogeneous Platforms, Proc. ACM SIGPLAN/SIGBED Conference on. Languages, Compilers, Tools and Theory for Embedded Systems (LCTES), Beijing, China, Jun 2012

 

Technical Reports

 

T1.              M. Moazeni, Y. Zou, M. Rofouei, A. Bui, M. Sarrafzadeh and J. Cong, A Performance Evaluation of General Purpose Applications on Multithreaded GPUs, UCLA Technical Report 090003

Publications before I came to UCLA

 

Now I am mainly working on domain specific computing using either FPGAs or GPUs.
The first application domain we target at is VLSI/CAD domains.
The second domain is medical imaging related.

 

 

 

free search engine submission service

html hit counter code