HB Suite

(Floorplanning Examples derived from the IBM benchmarks)

Director : Prof. Jason Cong

          Author : Michail Romesis

Copyright© 2004 the Regents of University of California



Circuit Description

The HB suite is developed at UCLA VLSI CAD LAB. A total of 18 floorplanning circuits are constructed from the IBM (ISPD’02) benchmarks. The circuits include both soft (reshapable) blocks and hard (fixed dimension) blocks. The soft blocks are generated by clustering standard cells according to their connectivity by repeated application of the First Choice algorithm. The soft blocks have fixed area and can be reshaped to aspect ratios in the range of [0.33, 3.0]. The hard blocks are the macros of the original benchmarks unchanged. The HB suite can be downloaded here.

Please direct your questions to michail@cs.ucla.edu.