J. Cong and W. Jiang, "Pattern-based Behavior Synthesis for FPGA Resource Reduction", Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, February 2008.
J. Cong and J. Xu, "Simultaneous FU and Register Binding Based on Network Flow Method", Design, Automation and Test in Europe (DATE 2008), Munich, Germany, March 2008.
J. Cong, G. Han, and W. Jiang, "Synthesis of an Application-Specific Soft Multiprocessor System ," Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2007.
J. Cong, Y. Fan, and W. Jiang, "Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture," Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2006.
J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "Platform-Based Behavior-Level and System-Level Synthesis," Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006. (Invited Paper)
J. Cong and Z. Zhang, "An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 433-438, July 2006.
J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang, "Behavior and Communication Co-Optimization for Systems with Sequential Communication Media," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.
D. Chen, J. Cong, Y. Fan and J. Xu, "Optimality Study of Resource Binding with Multi-Vdds," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 580-585, July 2006.
D. Chen, J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "xPilot: A Platform-Based Behavioral Synthesis System" SRC TechCon'05, Portland, OR, Nov, 2005.
J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng, "Bitwidth-Aware Scheduling and Binding in High-Level Synthesis," Proceedings of the Asia South Pacific Design Automation Conference, pp. 856-861, January 2005.
J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman and Z. Zhang, "Instruction Set Extension with Shadow Registers for Configurable Processors," Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 99-106, February 2005.
J. Cong, G. Han and Z. Zhang, "Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors," Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 263-270, November 2005.
J. Cong, Y. Fan, G. Han, and Z. Zhang, "Application-Specific Instruction Generation for Configurable Processor Architectures," Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 183 - 189, February 2004.
J. Cong, Y. Fan, and Z. Zhang, "Architecture-Level Synthesis for Automatic Interconnect Pipelining," Proceedings of the Design Automation Conference, pp. 602 - 607, June 2004.
J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang, "Architecture and Synthesis for On-Chip Multi-Cycle Communication," IEEE Transactions on Computer-Aided Design of Integrate d Circuits and Systems, pp.550 - 564, April 2004
D. Chen, and J. Cong, "Register Binding and Port Assignment for Multiplexer Optimization," Proceedings of the Asia Pacific Design Automation Conference, pp. 68 - 73, January 2004.
J. Cong, Y. Fan, X. Yang and Z. Zhang, "Architecture and Synthesis for Multi-Cycle Communication," ACM/SIGDA Proceedings of 2003 International Symposium on Physical Design, Monterey, California, pp. 190-196, April 2003.(Invited paper)
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