Yiping Fan's publications

4651 Boelter Hall
UCLA Computer Science Department
503 Hilgard
Los Angeles, CA 90095
Tel: 310-206-5449
Email: fanyp@cs.ucla.edu

Journal Publications

[J1] Fan Yi-Ping, Bei Jin-Song, Bian Ji-Nian, Xue Hong-Xi, Hong Xian-Long, "VERIS: an Efficient Model Checker for Synchronous VHDL Designs," Journal of Computer Aided Design, Computer Graphics (Chinese), vol.13, no.6, June 2001, pp. 485-9. Publisher: Science Press, China.

[J2] Jason Cong, Yiping Fan, Guoling Han, Xun Yang, and Zhiru Zhang, "Architecture and Synthesis for On-Chip Multicycle Communication," IEEE Transactions on Computer-Aided Design of Integrate d Circuits and Systems, pp. 550 - 564, April 2004. [pdf]

[J3] D. Chen, J. Cong, Y. Fan and L. Wan, "LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 18, Number 4, pp. 564-577, June 2009.

[J4] J. Cong, Y. Fan, and J. Xu, "Simultaneous Resource Binding and Interconnection Optimization Based on a Distributed Register-File Microarchitecture," ACM Transactions on Design Automation of Electronic Systems, Volume 14, Number 3, Article 35, pp.35:1-35:31, May 2009.


Conference Publications

[C1] Yiping Fan, Jinsong Bei, Jinian Bian, Hongxi Xue, Xianlong Hong, Jun Gu, "VERIS: An Efficient Model Checker for Synchronous VHDL Designs," Proceedings of 16th IFIP World Computer Congress - ICDA2000: Chip Design Automation, Beijing, China, Aug. 2000. [pdf]

[C2] Qiang Wu, Jinian Bian, Hongxi Xue, Yiping Fan, Weimin Wu, Xianlong Hong and Jun Gu, "Applying Search Space Smoothing Technique to Hardware/Software Partitioning," The 5th International Conference on ASIC (ASICON03), 2003, Beijing 85-88.

[C3] Zhong Chen, Jason Cong, Yiping Fan, Xun Yang, and Zhiru Zhang, "Pilot - A Platform-Based HW/SW Synthesis System for FPSoC," Workshop on Software Support for Reconfigurable Systems, Feb. 2003. [pdf]

[C4] Jason Cong, Yiping Fan, Xun Yang, and Zhiru. Zhang, "Architectural Synthesis for Multi-Cycle Communication," ACM/SIGDA Proceedings of 2003 International Symposium on Physical Design, Monterey, California, pp. 190-196, April 2003. [pdf]

[C5] Deming Chen, Jason Cong, Yiping Fan, "Low-Power High-Level Synthesis for FPGA Architectures," International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, pp. 134 - 139, Aug. 2003. [pdf]

[C6] Jason Cong, Yiping Fan, Guoling Han, Xun Yang, and Zhiru Zhang, "Architectural Synthesis Integrated with Placement for Multi-Cycle Communication," Proceedings of International Conference on Computer Aided Design, pp. 536-543, Nov. 2003. [pdf]

[C7] Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, and Jason Cong, "Gradual Relaxation Technique with Application to Behavioral Synthesis," Proceedings of International Conference on Computer Aided Design, pp. 529-535, Nov. 2003. [pdf] [ppt]

[C8] Jason Cong, Yiping Fan, Guoling Han, Xun Yang, and Zhiru Zhang, "Architecture and Synthesis for Multi-Cycle On-Chip Communication", Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis, 2003. [pdf]

[C9] J. Cong, Y. Fan, G. Han, and Z. Zhang, "Application-Specific Instruction Generation for Configurable Processor Architectures," Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 183 - 189, Feb. 2004. [pdf]

[C10] Jason Cong, Yiping Fan, and Zhiru Zhang, "Architecture-level Synthesis for Automatic Interconnect Pipelining," Proceedings of the Design Automation Conference, pp. 602 - 607, Jun. 2004. [pdf]

[ppt]

[C11] J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng, "Bitwidth-Aware Scheduling and Binding in High-Level Synthesis," Proceedings of the Asia South Pacific Design Automation Conference, Jan. 2005. [pdf]

[C12] Jason Cong, Yiping Fan, Guoling Han, Glenn Reinman, Zhiru Zhang, "Instruction Set Extension with Shadow Registers for Configurable Processors," Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, Feb. 2005. [pdf]

[C13] D. Chen, J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang, "xPilot: A Platform-Based Behavioral Synthesis System," Proceedings of SRC Techcon Conference, Oct. 2005.

[C14] J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang, "Behavior and Communication Co-Optimization for Systems with Sequential Communication Media," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.

[C15] D. Chen, J. Cong, Y. Fan and J. Xu, "Optimality Study of Resource Binding with Multi-Vdds," Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 580-585, July 2006.

[C16] J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "Platform-Based Behavior-Level and System-Level Synthesis (Invited Paper)," Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006.

[C17] J. Cong, Y. Fan, and W. Jiang, "Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture," Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2006.

[C18] D. Chen, J. Cong, Y. Fan and Z. Zhang, "High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs," IEEE/ACM Asia and South Pacific Design Automation Conference, Jan. 2007.


Book Chapters

[BC1] Z. Zhang, Y. Fan, W. Jiang, G. Han, C. Yang, and J. Cong, "AutoPilot: A Platform-Based ESL Synthesis System," "High-Level Synthesis: From Algorithm to Digital Circuit," ed. P. Coussy and A. Morawiec, Springer Publishers, 2008.

(c) Updated: Apr. 2, 2009.