3-D IC Physical Design and 3-D Architecture Exploration
Project Director: Prof.
3-D ICs have recently attracted great interest
from researchers and IC designers. Studies demonstrate a potential performance
improvement of up to 65% by transferring a placement from 2-D to 3-D and
eliminating long interconnects. Furthermore, the multiple device layer
structure of 3-D ICs provides a platform to integrate different components,
such as digital ICs, analog ICs, memory, RF modules, and different technologies
such as SOI, SiGe HBTs, GaAs, etc., into one single circuit stack. Thus,
it is a more flexible vehicle for system-on-chip (SoC) and system-in-package
(SiP) designs compared to planar 2-D IC technologies.
Although 3-D integration shows promise, significant
challenges associated with efficient circuit design and operation have
hampered its adoption and further development. The most important issue
in 3-D IC is heat dissipation. The thermal problem has already had an impact
on the reliability and performance of high-performance 2-D ICs. The problem
is aggravated in 3-D ICs, principally for two reasons: the devices are
more packed, which results in higher power density; and the insulating
dielectric layers between the device layers have much lower thermal conductivities
than silicon. Furthermore, the third dimension brings both flexibility
and difficulties to physical design algorithms. The existing 2-D metrics
cannot be simply extended to generate similar metrics for 3-D designs.
Take wirelength as an example: a ``bounding-cube'' might not have enough
accuracy for wirelength estimation because of the existence of huge obstacles
in z-direction. Also, a 3-D IC physical design problem is usually of higher
complexity, with a much enlarged solution space due to the multiple device
layer structure. Efficient 3-D physical designs tools, including 3-D floorplanning,
placement and routing tools, that are specifically designed to take the
thermal problem into consideration, are essential to 3-D IC circuit design.
The following figure shows the 3-D physical design
tool package that we are working on. Among the three major modules, we
have completed the initial version of the floorplanning and routing tools
and are working on the placement tool. Our group has also developed MEVA-3D,
an automated physical design and architecture performance estimation flow
for 3D architectural evaluation which includes 3D floorplanning, routing,
interconnect pipelining and automated thermal via insertion, and associated
die size, performance, and thermal modeling capabilities.
We are also exploring novel 3D architectures.
We have proposed the accelerator-over-processor computing platform as shown below.
The accelerators in this architecture are designed for a specific domain.
They can be shared among applications in the domain.
It provides an easy way to extend a general-purpose processor to a domain-specific professor with significant performance improvement and energy savings.
We also developed optimization methodologies to maximize the gain under any given area/bandwidth constraints.
J. Cong, A. Jagannathan, G. Reinman, and M. Romesis,
"Microarchitecture Evaluation with Physical Planning,"
Proc. of the Design Automation Conference,
Anaheim, pp. 32 - 36, June 2003.
J. Cong, A. Jagannathan, G. Reinman, and M. Romesis,
"Microarchitecture Evaluation with Physical Planning",
UCLA Technical Report.
J. Cong, J. Wei, and Y. Zhang,
"A Thermal-Driven Floorplanning Algorithm for 3D ICs,"
Proceedings of the International Conference on Computer-Aided Design,
A. Jagannathan, H. Yang, K. Konigsfeld, D. Milliron, M. Mohan, M. Romesis, G. Reinman, and J. Cong,
"Microarchitecture Evaluation and Optimization with Interconnect Pipelinning,"
Proc. of the Asia South Pacific Design Automation Conference,
Shanghai , China, January 2005.
J. Cong, and Y. Zhang,
"Thermal-Driven Multilevel Routing for 3-D ICs,"
Proceedings of the Asia South Pacific Design Automation Conference,
J. Cong and Y. Zhang,
"Thermal Via Planning for 3-D IC's,"
Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design,
San Jose, CA, November, 2005.
J. Cong, A. Jagannathan, Y. Ma, G. Reinman, J. Wei, and Y. Zhang,
"An Automated Design Flow for 3D Microarchitecture Evaluation,"
Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006),
Yokohama, Japan, January 2006, pp.384-389
J. Cong, G. Luo, J. Wei, and Y. Zhang,
"Thermal-Aware 3D IC Placement via Transformation,"
Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007),
Yokohama, Japan, pp. 780-785, January 2007.
J. Cong, Y. Ma, Y. Liu, E. Kursun, and G. Reinman,
"3D Architecture Modeling and Exploration,"
Proceedings of 24th International VLSI/ULSI Multilevel Interconnection Conference (VMIC),
Fremont, CA, pp. 231-238, September 2007.
Y. Liu, Y. Ma, E. Kursun, J. Cong, and G. Reinman,
"Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration,"
Proceedings of 25th IEEE International Conference on Computer Design,
Lake Tahoe, CA, pp. 259-266, October 2007.
- J. Cong, C. Liu, and G. Luo,
"Quantitative Studies of Impact of 3D IC Design on Repeater Usage,"
Proceedings of 25th International VLSI/ULSI Multilevel Interconnection Conference (VMIC),
Fremont, CA, pp. 344-348, October 2008.
J. Cong and G. Luo,
"A Multilevel Analytical Placement for 3D ICs,"
Proceedings of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009),
Yokohama, Japan, pp. 361-366, January 2009.
- J. Cong, K. Gururaj, M. Huang, S. Li, B. Xiao and Y. Zou, "Domain-Specific Processor with 3D Integration for Medical Image Processing", Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2011), Santa Monica, CA, pp. 247-250, September 2011.
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- 3D-Craft (UCLA 3D physical design flow) [linux]
- 3DFP-thermal-awear floorplanner for 3-D IC [solaris]
- TMARS-thermal-awear router for 3-D IC [linux rhep3.0]