People of the VLSI CAD Lab
Current Projects
System Level Design Automation
Logic and Physical Level Design Automation
Design Automation for Emerging Technologies
Past Projects
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Synthesis and Optimization Under Physical Hierarchy.
Sponsored
by SRC.
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Interconnect-Centric
Design Flow and Methodologies.
Sponsored by MARCO/GSRC, SRC, NSF, Intel.
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Interconnect Design and Optimization for High-Performance Mixed-Signal
MCM Layout.
Sponsored by Defense Advanced Research Project Agency (DARPA),
Electronic Technology Office (ETO).
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Advanced VLSI CAD Algorithms.
Sponsored by NSF Young Investigator Award.
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Computer-Aided Design of High Performance Wireless Networked Systems.
Sponsored by ARPA/CSTO.
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The Distributed Supercomputer Supernet -- A Multi-Service
Optical Intelligent Network.
Sponsored by ARPA/CSTO.
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Interconnect-Driven Layout Synthesis for Performance and Power Optimization.
Sponsored by Intel Corp.
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Logic Synthesis and Technology Mapping for FPGAs.
Sponsored by Xilinx, AT&T Bell Lab. and California MICRO Program.
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Performance and Power Optimization in VLSI Layout.
Sponsored by Fujitsu Laboratories Ltd.
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Rapid System Prototyping Using FPGA Technology.
Sponsored by Xerox Foundation.
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Clustering and Partitioning for Very Large-Scale Netlists.
Sponsored by Hewlett-Packard under California MICRO Program.
Publications
Software Release
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MPL
- A Multilevel Global Placement Tool
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mGP
- A Multilevel Global Placement Tool
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IPEM - Performance Estimation Models for Optimized Interconnects
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RASP - FPGA/CPLD Technology Mapping Package
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TRIO - Tree, Repeater and Interconnect Optimization Package
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V4R - Multilayer MCM Router
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MCAS - Multi-Cycle Architectural Synthesis System
- fpgaEva - A Heterogeneous FPGA Evaluation Tool
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Patoma - A Fast Floorplanner by Look-Ahead Enabled Recursive Bipartitioning
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SPCD - Simultaneous Placement with Clustering and Duplication for FPGAs
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xPilot
- A Platform-Based Behavioral Synthesis System
Links
Lab News
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