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People of the VLSI CAD Lab
- Faculty: Jason Cong, Miodrag Potkonjak, Majid Sarrafzadeh.
- Students
- Alumni
Current Projects
Customizable
Domain-Specific Computing
- Sponsored by NSF Expeditions
in Computing program.
- Year 3 Review Material: here
- Year 4 Review Material: here
System Level Design
Automation
- Platform
Architectures Sponsored by MARCO/DARPA,
- Tools and Methodologies for System-on-a-Chip(SOC)
Designs. Sponsored by NSF
Logic
and Physical Level Design Automation
- Optimality study of VLSI CAD algorithms Sponsored by SRC.
- Highly-Scalable Placement Algorithms. Sponsored by SRC, NSF.
- FPGA
Synthesis and Technology Mapping. Sponsored by NSF, Altera and Xilinx
under CA MICRO and Discovery Program.
Design Automation for
Emerging Technologies
- International Center on Design for Nanotechnologies.
Sponsored by NSF.
- 3-D
IC Physical Design and 3-D Architecture Exploration. Sponsored
by DARPA and CFDRC.
- Design Exploration of RF Interconnects in
Future Chip Multi-Processors. Sponsored by SRC.
Open-Source Accelerators Store
Open-Source Large RTL Design
PolyOptHLS
Acknowledgements
Past Projects
- Microarchitecture Evaluation. Sponsored by NSF, GSRC, Intel.
- Multilevel Full-Chip
Gridless Routing System.
- RIMatch and
other Boolean Matching Improvements.
- Ports for
GRLIB LEON3 implementation on BEE2 and ASIC.
- Synthesis
and Optimization Under Physical Hierarchy. Sponsored by SRC.
- Interconnect-Centric
Design Flow and Methodologies. Sponsored by MARCO/GSRC, SRC, NSF,
Intel.
- Interconnect Design and Optimization for
High-Performance Mixed-Signal MCM Layout. Sponsored by Defense Advanced
Research Project Agency (DARPA), Electronic Technology Office (ETO).
- Advanced VLSI CAD Algorithms. Sponsored by NSF
Young Investigator Award.
- Computer-Aided Design of High Performance
Wireless Networked Systems. Sponsored by ARPA/CSTO.
- The Distributed Supercomputer Supernet -- A
Multi-Service Optical Intelligent Network. Sponsored by ARPA/CSTO.
- Interconnect-Driven Layout Synthesis for
Performance and Power Optimization. Sponsored by Intel Corp.
- Logic Synthesis and Technology Mapping for FPGAs.
Sponsored by Xilinx, AT&T Bell Lab. and
- Performance and Power Optimization in VLSI
Layout. Sponsored by Fujitsu Laboratories Ltd.
- Rapid System Prototyping Using FPGA Technology.
Sponsored by Xerox Foundation.
- Clustering and Partitioning for Very Large-Scale
Netlists. Sponsored by Hewlett-Packard under
Publications
- Publications from
Professor Jason Cong's group.
Software Release
- 3D-Craft
- A Physical Design Flow for 3D ICs
- MPL
- A Multilevel Global Placement Tool
- mGP
- A Multilevel Global Placement Tool
- IPEM
- Performance Estimation Models for Optimized Interconnects
- RASP
- FPGA/CPLD Technology Mapping Package
- TRIO
- Tree, Repeater and Interconnect Optimization Package
- V4R - Multilayer MCM Router
- MCAS - Multi-Cycle Architectural Synthesis
System
- fpgaEva - A Heterogeneous FPGA Evaluation
Tool
- Patoma
- A Fast Floorplanner by Look-Ahead Enabled Recursive Bipartitioning
- SPCD
- Simultaneous Placement with Clustering and Duplication for FPGAs
- xPilot -
A Platform-Based Behavioral Synthesis System
Links
- UCLA EE
Department Design Automation Lab
- About SIGDA Publications on CD-ROM
- Oxford
University Computing Laboratory
- UC
Berkeley Design Technology Wareho use
- MCNC Home Page
- Frontiers in Semiconductor Research
- The National
Technology Roadmap for Semiconductors
- WWW
Computer Architecture Home Page
- ACM, The First
Society in Computing
- IEEE Computer
Society
- ACM
Transactions on Design Automation of Electronic Systems
- IEEE Design
& Test of Computers
- IEEE Spectrum
- IEEE
Transactions on VLSI Systems
- ACM
SIG Proceedings
- Design Automation
Conference
- ICCAD
- FPGA
- Design,
Automation and Test in Europe
- ASP-DAC
- Design
Automation Cafe
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